Memory controller for synchronous burst transfers
AssigneeIntel Corporation
InventorsDaniel Litaize, Jean-Claude Salinier, Abdelaziz Mzoughi, Fatima-Zahra Elkhlifi, Mustapha Lalam, Pascal Sainrat
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Abstract
A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.
Claims29
A multiprocessor system, of the type comprising a central memory (RAM) organized in blocks of information (bi), treatment processors (CPU1 . . . CPUj . . . CPUn), a cache memory (MCj) connected to each treatment processor (CPUj) and organized in blocks of information (bi) of the same size as those of the central memory, a directory (RGj) and its management processor (PGj) associated with each cache memory (MCj), means for communicating addresses of blocks between processors (CPUj) and the central memory (RAM), said multiprocessor system being characterized in that it is provided with:
- an assembly of shift registers, called memory registers (RDM1 . . . RDMj . . . RDMn) each register (RDMj) of this assembly being connected to the central memory (RAM) in such a manner as to permit, in one cycle of this memory, a parallel transfer in read or write of a block of information (bi) between said register and said central memory,
- shift registers, called processor registers (RDP1 . . . RDPj . . . RDPn), each processor shift register (RDPj) being connected to the cache memory (MCj) of a processor (CPUj) in such a manner as to permit a parallel transfer in read or write of a block of information (bi) between said shift register (RDPj) and said cache memory (MCj),
- an assembly of series links (LS1 . . . LSj . . . LSn), each connecting a memory shift register (RDM) and a processor shift register (RDPj) and adapted to permit the transfer of blocks of information (bi) between the two registers considered (RDMj, RDPj)
A multiprocessor system as in one of claims 1 to 111 characterized in that:
- several processor shift registers (RDPk, RDPk+1 . . . ) corresponding to a given assembly of processors (CPUk, CPUk+1 . . . ) are connected in parallel to a same series link (LSk), a local arbitrator being associated with each assembly of processors (CPUk, CPUk+1 . . . ) in order to arbitrate access conflicts to the series link (LSk),
- a memory management processor is connected to block address communication means and to the central memory (RAN) and comprises coding means adapted to associate with each block of information (BI) a leading identification of the processor concerned among each assembly (CPUk, CPUk+1 . . . ) sharing a series link (LSk),
- management processors (PGk, PGk+1 . . . ) associated with the cache memories (MCk, MCk+1 . . . ) of the processors of said assembly (CPUk, CPUk+1 . . . ) comprising decoding means for the leading identification.
A process for the exchange of information between a central memory (RAM) organized in blocks of information (bi) and processors (CPU1 . . . CPUj . . . CPUn) each provided with a cache memory (MCj) organized in blocks of the same size (bi), and a directory (RG) and its management processor (PGj), in such a manner that the exchange between the central memory (RAM) and each processor (CPUj) is carried out via the cache memory (MCj) of the latter, said process being characterized in that each transfer of a block of information (bi) from the central memory (RAM) to the cache memory (MCj) of a given processor consists of:
- transferring in one cycle of the central memory, the block (bi) of said central memory (RAM) to a memory shift register (RDMj) of the size of one block, making part of an assembly of shift registers (RDM1 . . . RDMj . . . RDMn) connected to the central memory,
- transferring on a series link (LSj) the contents of the memory shift register (RDMj) to a processor shift register (RDPj) of the same capacity, associated with the cache memory (MCj) of the processor considered (CPUj),
- transferring the contents of said processor shift register (RDPj) to said cache memory (MCj).
A process for the exchange of information between a central memory (RAM) organized in blocks of information (bi) and processors (CPU1 . . . CPUj . . . CPUn) each provided with a cache memory (MCj) organized in blocks of the same size (bi), and a directory (RGj) and its management processor (PGj), in such a manner that the exchange between the central memory (RAM) and each processor (CPUj) is carried out by the cache memory (MCj) of the latter, said process being characterized in that each transfer of a block of information (bi) from the cache memory (MCj) of a given processor (CPUj) to the central memory consists of:
- transferring the block (bi) of said cache memory considered (MCj) to a processor shift register (RDPj) of the size of one block, associated with said cache memory (MCj),
- transferring on a series link (LSj) the contents of the processor shift register (RDPj) to a memory shift register (RDMj) of the same capacity, provided to the processor considered in an assembly of shift registers (RDM1 . . . RDMj . . . RDMn) connected to the central memory (RAM),
- transferring in one cycle of the central memory the contents of the memory shift register (RDMj) to said central memory (RAM).
Dependencies are inferred from the claim text.