Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor

In a system for addressing sequential data packets from a plurality of input data line cards to enable their memory storage in successive shared memory block sections of an output-buffered switch fabric, each assigned to a queue dedicated for an output port, an address generator having, in combination with said system, a plurality of similar subaddress generators successively connected in a closed ring structure and each capable of assigning addresses for predetermined size byte packets of input data traffic received in a plurality of successive time slots, to produce packet composition into super packets that are ordered based on time of arrival;

• means for sequentially allocating memory in the shared memory sections from subaddress generator to subaddress generator along said ring by allocating a continuous memory block for a super packet by assigning an initial starting address in a destination queue from a subaddress generator, and thereupon generating the starting address of the next super packet by adding the super packet size to said initial starting address, and moving to the next subaddress generator sequentially along the subaddress generator ring;
• and packet decomposing means operable upon the assigning of an address for each super packet, for simultaneously assigning addresses for the individual packets in the super packet, based on their arrival order.

20 The address generator of claim 19 wherein the address assigning capability extends for 64 packets every 40 ns, as when all packets belong to the same queue.

An address generator for addressing sequential data packets to enable their storage, having, in combination, a plurality of similar subaddress generators successively connected in a closed ring structure and each capable of assigning addresses for predetermined size byte data packets received in a plurality of successive time slots, producing packet composition into super packets that are ordered, based on time of arrival;

• means for sequentially allocating memory from subaddress generator to subaddress generator along said ring for a super packet by assigning an initial starting address in a destination queue from a subaddress generator, and thereupon generating the starting address of the next super packet by adding the super packet size to said initial starting address, and moving to the next subaddress generator sequentially along the subaddress generator ring;
• and packet decomposing means operable upon the assigning of an address for each super packet, for simultaneously assigning addresses to the individual packets in the super packet, based on their arrival order.

The method of addressing sequential data packets to enable their memory storage, that comprises, connecting a plurality of similar subaddress generators successively in a closed ring structure, with each subaddress generator being capable of assigning addresses for predetermined size data byte packets of input data traffic received in a plurality of successive time slots to produce packet composition into super packets that are ordered based on time of arrival;

• allocating a continuous memory block for a super packet by assigning an initial starting address in a destination queue from a subaddress generator;
• thereupon generating a starting address for the next super packet by adding the super packet size to the said initial starting address, and moving to the next subaddress generator sequentially along the subaddress generator ring;
• and, upon the assigning of an address for each super packet, producing packet decomposition at the corresponding subaddress generator by simultaneously assigning addresses for the individual packets in the super packet, based on their arrival order.

A sequential data packet addressing method, particularly adapted for shared memory output-buffered switch fabrics and related memories, that comprises, using a ring of successive subaddress generators to each assign addresses for predetermined size data byte packets received in successive time slots;

• creating therefrom super packets ordered based on arrival time;
• sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets;
• and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.