Address range checking circuit and method of operation

A data processor comprising:

• a stack cache having 2N address locations beginning at a base address location, B[M:0], for storing data values being processed by said data processor;
• and
• an address range checking circuit capable of determining if a target address A[M:0] is within said stack cache, said address range checking circuit comprising:
• comparison circuitry capable of determining if the address segment A[N−1:0] is less than the address segment B[N−1:0] and generating on an output a first control signal having a first logic state indicating A[N−1:0] is less than B[N−1:0] and having a second logic state indicating A[N−1:0] is not less than B[N−1:0];
• first equivalence detection circuitry capable of determining if the address segment A[M:N] is equal to the address segment B[M:N] and generating on an output an A=B status signal having a first logic state indicating A[M:N] is equal to B[M:N] and having a second logic state indicating A[M:N] is not equal to B[M:N];
• second equivalence detection circuitry capable of determining if the address segment A[M:N] is equal to the address segment B[M:N] plus one and generating on an output an A=B+1 status signal having a first logic state indicating A[M:N] is equal to B[M:N] plus one and having a second logic state indicating A[M:N] is not equal to B[M:N] plus one;
• and
• a multiplexer controlled by said first control signal generated by said comparison circuitry, said multiplexer having a first input coupled to said first equivalence detection circuitry output and a second input coupled to said second equivalence detection circuitry output, wherein said first control signal causes said multiplexer to output said A=B status signal when said first control signal is at said second logic state indicating A[N−1:0] is not less than B[N−1:0] and causes said multiplexer to output said A=B+1 status signal when said first control signal is at said first logic state indicating A[N−1:0] is less than B[N−1:0].

A method of determining if a target address A[M:0] is within an address space having 2N address locations beginning at a base address location, B[M:0], the method comprising the steps of:

• determining if the address segment A[N−1:0] is less than the address segment B[N−1:0] and generating a first control signal having a first logic state indicating A[N−1:0] is less than B[N−1:0] and having a second logic state indicating A[N−1:0] is not less than B[N−1:0];
• determining if the address segment A[M:N] is equal to the address segment B[M:N] and generating an A=B status signal having a first logic state indicating A[M:N] is equal to B[M:N] and having a second logic state indicating A[M:N] is not equal to B[M:N];
• determining if the address segment A[M:N] is equal to the address segment B[M:N] plus one and generating an A=B+1 status signal having a first logic state indicating A[M:N] is equal to B[M:N] plus one and having a second logic state indicating A[M:N] is not equal to B[M:N] plus one;
• if the first control signal is at the second logic state indicating A[N−1:0] is not less than B[N−1:0], selecting the A=B status signal, wherein the A=B status signal having the first logic state indicates that the target address A[M:0] is within an address space having 2N address locations;
• and
• if the first control signal is at the first logic state indicating A[N−1:0] is less than B[N−1:0], selecting the A=B+1 status signal, wherein the A=B+1 status signal having the first logic state indicates that the target address A[M:0] is within an address space having 2N address locations.