Method for providing concurrent non-blocking heap memory management for fixed sized blocks
OwnerThomas J. Bonolainventor
Life of this patent
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Abstract
The specification discloses a heap memory management system in which software streams remove and replace blocks of heap memory from the heap pile, managed in a linked list fashion, in a last-in/first-out fashion at the top of the list. A hardware device returns blocks of heap memory, and this return is to the end or bottom of the linked list. In this way, software streams may remove and return blocks of heap memory simultaneously with hardware devices returning blocks of heap memory.
Claims38
In a computer system executing a software stream that removes a block of heap memory from a heap pile for use by a hardware device, a method comprising:
- returning the block of heap memory to the heap pile by the hardware device.
A method of managing a heap memory comprising:
- maintaining unused blocks of heap memory as a linked list, and wherein the unused blocks of the linked list comprise a first block at a beginning of the linked list, a second block pointed to the first block, and a third block at an end of the linked list;
- removing, by a software stream, the first block from the linked list, thus making the second block the beginning of the linked list;
- and
- returning, by a hardware device, a return block to the linked list by placing the return block at an end of the linked list.
A method of managing a heap memory in a computer system, the method comprising:
- allowing a software thread to add and remove blocks of heap memory from a linked list of free blocks of heap memory in a last-in/first-out (LIFO) fashion at a first end of the linked list;
- and
- allowing a hardware device to add blocks of heap memory to the linked list of free blocks of heap memory at a second end of the linked list.
A computer system comprising:
- a microprocessor executing a software stream;
- a main memory array, a portion of the main memory array allocated to be a heap memory, and unused portions of the heap memory part of a heap pile;
- a first bridge logic device coupling the microprocessor to the main memory array;
- a hardware device coupled to the heap memory through the first bridge logic device;
- a graphics card coupled to the first bridge logic device, and also coupled to a video display device;
- wherein the software stream executed on the microprocessor removes blocks of heap memory from the heap pile for use by the hardware device;
- and
- wherein the hardware device returns blocks of heap memory to the heap pile without intervention from the software stream executed by the microprocessor.
Dependencies are inferred from the claim text.