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OwnerGlenn Ashley Farrall, Neil Stuart Hastie +1inventors
InventorsGlenn Ashley Farrall, Neil Stuart Hastie, Erik Karl Nordan
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An electronic processing device has an integer pipeline and a load/store pipeline disposed in parallel to receive a series of instructions via a Fetch stage and a Predecode stage. If an instruction is stalled in a Decode stage of the integer pipeline, one or more Delay stages can be switched into and out of the integer pipeline between the Decode stage and the Predecode stage so as to increase or decrease its effective length. This allows the Predecode stage to continue to issue instructions and therefore the load/store pipeline does not need to stall. The maximum number of delay stages that need to be available for switching into the integer pipeline is the same as a load-use penalty for that pipeline.
An electronic processing device, comprising:
The electronic processing device according to claim 2, wherein said pipeline has a predecode stage and a decode stage, and said delay stage is switched into said pipeline between said predecode stage and said decode stage.
A method of pipelining in an electronic processing device having at least two pipelines disposed in parallel to receive a series of instructions, each pipeline having a plurality of stages through which the instructions pass, which comprises the steps of:
Dependencies are inferred from the claim text.