Apparatus and method for exiting from a software pipeline loop procedure in a digital signal processor

A multiple execution unit processor, the processor comprising:

• a memory unit storing a plurality of execution packets;
• a buffer storage unit for storing the execution packets;
• a dispatch unit for directing each instruction of an execution packet applied thereto to an preselected execution unit;
• and
• a program memory control unit for retrieving an execution packet from the memory unit, the program memory unit having a first state wherein an execution packet from the memory unit is applied to the dispatch unit and to the buffer storage unit, the execution packet applied to the execution unit being stored therein, wherein in the first state the retrieved execution packet and any corresponding execution packet stored in the buffer storage unit are applied to the dispatch unit simultaneously, the program control memory unit having a second state wherein the execution packets stored in the buffer storage unit are simultaneously applied to the dispatch unit, the program control memory unit having a third state wherein after the earliest stored execution packet in the buffer storage unit is eliminated after each application to the crossbar unit, the program control memory unit responsive to a first instruction for terminating a software pipeline loop procedure upon identification of a preselected condition.