Method for reducing cache conflict Misses
AssigneeSun Microsystems, Inc.
InventorDavid P. Stoutamire
Life of this patent
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Abstract
An invention is provided for reducing cache conflict misses via specific placement of non-split functions and data objects in main memory based on cache size. A cache size of a computer cache memory is determined, and a first data block is placed within a main computer memory. The first data block includes a first sub-block that will be frequently referenced. In addition, the first sub-block ends at a first ending address. A second data block is then placed within the main computer memory. The second data block includes a second sub-block that will be frequently referenced, and is placed such that the second sub-block will be contiguous with the first sub-block in the computer cache memory during execution.
Claims20
A method for reducing computer cache conflict misses, comprising the operations of:
- determining a cache size of a computer cache memory;
- placing a first data block within a main computer memory, wherein the first data block includes a first sub-block that will be frequently referenced, and wherein the first sub-block ends at a first ending address;
- and
- placing a second data block within the main computer memory, the second data block including a second sub-block that will be frequently referenced, wherein the second data block is placed such that the second sub-block will be contiguous with the first sub-block in the computer cache memory during execution.
A computer program embodied on a computer readable medium for reducing computer cache conflict misses, comprising:
- a code segment that places a first data block within a main computer memory, wherein the first data block includes a first sub-block that will be frequently referenced, and wherein the first sub-block ends at a first ending address;
- and
- a code segment that places a second data block within the main computer memory, the second data block including a second sub-block that will be frequently referenced, wherein the second data block is placed such that the second sub-block is located at a main memory address that is a multiple of a cache size of computer cache from the first ending address.
A method for reducing computer cache conflict misses, comprising the operations of:
- determining a cache size of a computer cache memory;
- placing a first data block within a main computer memory, wherein the first data block includes a first sub-block that will be frequently referenced, and wherein the first sub-block ends at a first ending address;
- and
- placing a second data block within the main computer memory, the second data block including a second sub-block that will be frequently referenced, wherein the second data block is placed such that the second sub-block is located at a main memory address that is a multiple of the cache size from the first ending address.
Dependencies are inferred from the claim text.