Ferroelectric memory device and method of reading a ferroelectric memory

A ferroelectric memory device comprising:

• at least two adjacent ferroelectric subarrays, each subarray comprising:
• a plurality of ferroelectric memory cells disposed in multiple rows and multiple columns of a two-dimensional array;
• a plurality of bitlines coupled to the ferroelectric memory cells of respective columns of the multiple columns, the bitlines of the plurality numbered sequentially in even/odd sequence;
• a first multiplexer coupled to the even bitlines of the plurality of bitlines of each subarray, the first multiplexer disposed on a first side of the subarrays;
• a second multiplexer coupled to the odd bitlines of the plurality of bitlines of each subarray, the second multiplexer disposed on a second side of the subarrays, the second side opposite the first side;
• and
• first and second sense amplifiers disposed on the first and second opposite sides of the subarrays;
• the first sense amplifiers to receive signals from the first multiplexer;
• and
• the second sense amplifier to receive signals from the second multiplexer.

A method of reading a ferroelectric memory array, comprising:

• addressing a select subarray of the ferroelectric memory array, the subarray defined as a group of contiguous columns of the memory array;
• addressing a select row of the ferroelectric memory array;
• and
• defining a select group of ferroelectric cells in accordance with the select row and the select subarray;
• and
• using the select group of ferroelectric cells to read data therefrom, wherein the reading comprises accessing the ferroelectric cells of the select group concurrently.

A method of reading a ferroelectric memory device, comprising:

• decoding a column address to select a subarray of the ferroelectric memory device;
• enabling the select subarray by biasing the first electrodes of the ferroelectric memory cells of the addressed subarry with a low level voltage and configuring the rows of the ferroelectric memory cells of the addressed subarray to be driven in accordance with signals of a plurality of global wordlines;
• substantially concurrent with the enabling, biasing the plurality of global wordlines to drive the second electrodes of the ferroelectric cells of the select subarray with voltage levels substantially the same as the low level voltage;
• decoding a row address to define a select global wordline of the plurality;
• after the enabling, activating the select global wordline to apply a read level voltage to the second electrodes of a row of ferroelectric cells of the select subarray.

A method of writing a ferroelectric memory, comprising:

• biasing bitlines of the ferroelectric memory with a first quiescent level;
• biasing passive wordlines of the ferroelectric memory with a second quiescent level;
• and
• driving bitlines of the ferroelectric memory with bias levels dependent upon write data.