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US 2003/0120843 A1Published application
Output data path capable of multiple data rates
AssigneeMicron Technology, Inc.
InventorsJohn D. Porter, William N. Thompson, Larren Gene Weber
Life of this patent
Estimating the term…
Abstract
Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.
Claims43
A device comprising:
- a data unit;
- an output register connected to the data unit;
- a holding register connected to the data unit and the output register;
- an output buffer connected to the output register and the holding register;
- and
- a selection mechanism connected to the output register and the holding register for selecting a data rate between a first data rate and a second data rate for data outputted at the output buffer.
3 more elements
A device comprising:
- a data unit;
- a first path connected to the data unit;
- a second path connected to the data unit;
- an output register connected to the first path and the second path;
- and
- a holding register connected to the first path, the second path, and the output register
- a selection mechanism connected to the output register and the holding register for selecting a data rate between a single data rate and a double data rate;
- wherein in the double data rate, the output register is configured to receive a first piece of data from the first path on a first edge of a clock signal and configured to receive a second piece of data from the holding register on a second edge of the clock signal;
- and
- wherein in the single data rate, the output register is configured to receive the first piece of data from the first path on the first edge of the clock signal and configured to receive the first piece data from the holding register on the second edge of the clock signal.
7 more elements
A device comprising:
- a data unit;
- a first path connected to the data unit;
- a second path connected to the data unit;
- an output register connected to the first path and the second path for receiving data from one of the first path and the second path on a first edge of a clock signal;
- and
- a holding register connected to output register, the first path and the second path for receiving data from one of the first path and the second path on the first edge of a clock signal and for passing the data to the output register on a second edge of the clock signal.
3 more elements
A device comprising:
- a data unit including a first range of data and a second range of data;
- a first multiplexor (mux) connected to the data unit for selecting the first range of data;
- a second mux connected to the data unit for selecting the second range of data;
- an output register connected to the first mux and the second mux for receiving data from the data unit;
- a holding register connected to the first mux and the second mux for receiving data from the data unit and for passing the data to the output register;
- an output buffer connected to the output register;
- and
- a tripulse buffer connected to the output register for placing a double zero into the output register and the holding register to place the output buffer into a tri-state condition.
5 more elements
A device comprising:
- a data unit;
- an output register connected to the data unit;
- a holding register connected to the data unit and the output register;
- a select pin connected to the output register and the holding register for selecting a data rate between a first data rate and a second data rate;
- wherein in the first data rate, the output register is configured to receive a first piece of data from the data unit on a first edge of a clock signal and configured to receive a second piece of data from the holding register on a second edge of the clock signal;
- and
- wherein in the second data rate, the output register is configured to receive the first piece of data from the data unit on the first edge of the clock signal and configured to receive from the holding register a piece of data having the same data as the first piece of data on the second edge of the clock.
4 more elements
A system comprising:
- a processor;
- a data unit having memory cells;
- an output register connected to the data unit;
- a holding register connected to the data unit and the output register;
- an output buffer connected to the output register and the holding register for outputting data from the memory cells to the processor;
- and
- a selection mechanism connected to the output register and the holding register for selecting a data rate between a first data rate and a second data rate for data outputted at the output buffer.
4 more elements
A method comprising:
- selecting a data rate among multiple data rates for transferring data;
- transferring a first piece of data to an output register on a first edge of a clock signal;
- outputting the first piece of data from the output register;
- transferring a second piece of data to a holding register on the first edge of the clock signal;
- transferring the second piece of data from the holding register to the output register on a second edge of the clock signal;
- and
- outputting the second piece of data from the output register.
4 more elements
A method comprising:
- selecting a data rate among multiple data rates for transferring data;
- passing a first piece of a first data set to an output register;
- passing a first piece of a second data set to the holding register;
- outputting the first piece of the first data set from the output register;
- passing the first piece of the second data set from the holding register to the output register;
- outputting the first piece of the second data set from the output register;
- passing a second piece of the first data set to the output register;
- passing a second piece of the second data set to a holding register;
- outputting the second piece of the first data set from the output register;
- passing the second piece of the second data set from the holding register to the output register;
- and
- outputting the second piece of the second data set from the output register.
9 more elements
A method comprising:
- selecting a data rate among multiple data rates for transferring data;
- transferring a first data bit from a data array to an output register;
- transferring a second data bit from the data array to a holding register;
- passing the second data bit from the holding register to the output register;
- transferring a first subsequent data bit from the data array to the output register,
- transferring a second subsequent data bit from the data array to the holding register;
- passing the second subsequent data bit from the holding register to the output register;
- and
- outputting from the output register the first data bit, the subsequent first data bit, the second data bit, and the subsequent second data bit on consecutive edges of a clock signal.
6 more elements
Dependencies are inferred from the claim text.