Receiver multi-protocol interface and applications thereof

A multiple processor integrated circuit comprises:

• a plurality of processing units;
• cache memory;
• memory controller operably coupled to system memory;
• internal bus operably coupled to the plurality of processing units, the cache memory and the memory controller;
• packet manager operably coupled to the internal bus;
• node controller operably coupled to the internal bus;
• first configurable packet-based interface;
• second configurable packet-based interface;
• and
• switching module operably coupled to the packet manager, the node controller, the first configurable packet-based interface, and the second configurable packet-based interface, wherein each of the first and second configurable packet-based interfaces include a input/output module and a media access control (MAC) layer module, wherein the input/output module includes:
• a wide bandwidth amplifier operable to amplify a first formatted input signal or a second formatted input signal to produce an amplified input signal;
• data sampling module operably coupled to convert the amplified input signal into a first data stream in accordance with at least one first sampling clock signal when the multi-protocol interface is in a first operational mode and to convert the amplified input signal into a second data stream in accordance with at least one second sampling clock signal when the multi-protocol interface is in a second operational mode;
• and
• clocking module operably coupled to generate the at least one first sampling signal from a reference clock when the multi-protocol interface is in the first operational mode and to generate the at least one second sampling clock signal based on the reference clock when the multi-protocol interface is in the second operational mode.