Low-power Booth-encoded array multiplier
AssigneeThe Regents of the University of California
InventorsAlan N. Willson JR., Zhan Yu, Larry S. Wasserman
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Abstract
An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.
Claims68
An array multiplier, comprising:
- a partial-product generator;
- an adder array;
- and
- means for reducing power dissipation in said adder array compared to a standard array multiplier.
An array multiplier, comprising:
- a partial-product generator;
- an adder array;
- and
- means for reducing power dissipation in said adder array by adding partial-products according to their transition probabilities.
An array multiplier, comprising:
- a partial-product generator;
- and
- an adder array configured to add partial-partial products according to their transition probabilities.
In an array multiplier, the improvement comprising:
- an adder array configured to sequentially add partial-products from a partial-product generator according to their transition probabilities.
In an array multiplier having a partial product generator and an adder array, the improvement comprising:
- configuring the adder array to add partial-products according to their transition probabilities.
An array multiplier circuit configured to add partial-products according to their transition probabilities.
A method of reducing power dissipation in an array multiplier circuit, comprising:
- configuring said circuit to add partial-products according to their transition probabilities.
Dependencies are inferred from the claim text.