Clock skew measurement circuit on a microprocessor die

A microprocessor, comprising:

• a clock domain region having a target clock;
• a jitter measurement circuit associated with the clock domain region;
• and
• wherein the jitter measurement circuit measures an uncertainty window within which the cache clock makes state transitions.

A method of measuring an uncertainty window within which a target clock signal on a microprocessor die makes state transitions, the method comprising:

• generating on the microprocessor die a first and second reference clock signals having the same frequency but differing in phase relationship;
• defining a time window between features of the first and second reference clock signals;
• comparing on the microprocessor die a plurality of cycles of the target clock signal to the reference clock signals to determine whether the target clock signal makes state transitions within the time window;
• adjusting the time window;
• and
• repeating the comparing step and adjusting step to determine the uncertainty window.

A system for measuring an uncertainty window of a target clock signal of a microprocessor, the system comprising:

• a measurement circuit on the die of the microprocessor;
• an external measurement system coupled the measurement circuit by way of a scan chain of the microprocessor, and wherein the external measurement system executes software adapted to control the measurement circuit through the scan chain;
• wherein the external measurement system is further adapted to adjust a phase relationship of a plurality reference clock signals having varying phase, the plurality of reference clock signals define a plurality of time windows between corresponding features;
• and
• wherein the measurement circuit compares the target clock signal to the plurality of time windows to determine the uncertainty window of the target clock signal.

In system for measuring on the die of the electronic device an uncertainty window within which a target clock signal may make a state transition, a method of calibrating a measurement circuit comprising:

• generating a first and second calibration signal, each calibration signal having the same frequency, but differing in phase relationship by a known period of time;
• phase locking an output signal of a programmable delay chain to the first calibration signal;
• noting a number of programmable taps required to phase lock to the first calibration signal;
• phase locking the output signal of the programmable delay chain to the second calibration signal;
• noting the number of programmable taps required to phase lock to the second calibration signal;
• attributing the difference in the number of taps to lock to the first and second calibration signal to the known period of time;
• and thereby
• attributing to each tap a portion of the known period of time.

A microprocessor comprising:

• a core region adapted to execute software routines;
• a cache region acting as a working memory for the core region, and the cache region also having a cache clock;
• and
• a measurement means on the microprocessor die for determining skew and jitter of the cache clock.

A method for determining an uncertainty window within which a target clock signal of an electronic device makes state transitions, the method comprising:

• generating on a microprocessor die a first, second, third and fourth reference clock signals having the same frequency but differing in phase relationship;
• defining a first time bin between respective features of the first and second reference clock signals, defining a second time bin between respective features of the second and third reference clock signals, and defining a third time bin between respective features of the third and fourth reference clock signals;
• comparing on the microprocessor die a plurality of cycles of the target clock signal to the reference clock signals to determine in which bin the target clock signal makes it state transitions;
• adjusting the phase relationship of at least one of the reference clock signals, and thereby adjusting the time width of at least one time bin;
• and
• repeating the adjusting step and the comparing step until the uncertainty window is determined.

A microprocessor, comprising:

• a cache region having a cache clock;
• a jitter measurement circuit associated with the cache region, wherein the jitter measurement circuit measures an uncertainty window within which the cache clock makes state transitions;
• wherein the jitter measurement circuit further comprises:
• four delay units creating a four reference clock signals, each reference clock signal having the same frequency but differing in phase relationship;
• a measurement unit coupled to the four reference clock signals and the cache clock, and wherein the measurement unit compares the cache clock to the plurality of reference clock signals to determine the uncertainty window of the cache clock;
• and
• a calibration unit coupled to the delay unit and configured to provide signals for calibration of the jitter measurement unit.