Method and apparatus for digital frequency synthesis

A digital frequency synthesizer comprising:

• one or more delay lines including a plurality of output taps;
• one or more clock signal sources coupled to the one or more delay lines;
• one or more multiplexers including:
• a plurality of signal inputs coupled to the plurality of output taps;
• a plurality of address inputs;
• and
• a common output;
• a controller including a plurality of control signal outputs coupled to the plurality of address inputs, for causing the one or more multiplexers to couple a plurality of output taps to the common output during each of a plurality of periods of a clock signal generated by at least one of the one or more clock signal sources.

A digital frequency synthesizer comprising:

• a common output;
• a plurality of clock signal sources;
• a plurality of delay lines each of which include;
• a delay line input coupled to one of the plurality of clock signal sources;
• a plurality of delay line taps;
• a plurality of multiplexers each of which include:
• a plurality of multiplexer inputs coupled to the delay line taps of one of the plurality of delay lines;
• one or more multiplexer address inputs;
• and
• a multiplexer output coupled to the common output.

A digital frequency synthesizer comprising:

• a clock signal source for outputting a clock signal at a first frequency;
• a delay line including:
• a delay line input coupled to the clock signal source;
• and
• a plurality of delay line output taps each of which is separated from the delay line input by a predetermined delay;
• a common output;
• a means for selectively coupling two or more output taps to the common output during a plurality of periods of the clock signal;
• whereby a signal at a second frequency that exceeds the first frequency is output at the common output.

A wireless communication device comprising:

• a mixer including:
• a first input for receiving a first signal that includes coded information;
• a second input for receiving a locally generated signal for mixing with the first signal;
• a digital frequency synthesizer including:
• one or more delay lines including a plurality of output taps;
• one or more clock signal sources coupled to the one or more delay lines;
• one or more multiplexers including:
• a plurality of signal inputs coupled to the plurality of output taps;
• a plurality of address inputs;
• and
• a common output coupled to the second input of the mixer;
• and
• a controller including a plurality of control signal outputs coupled to the plurality of address inputs, for causing the one or more multiplexers to couple a plurality of output taps to the common output during a plurality of periods of a clock signal generated by at least one of the one or more clock signal sources.

A digital frequency synthesizer comprising:

• a clock signal source for outputting a clock signal that is characterized by a clock signal period;
• a first delay line including:
• a first delay line input coupled to the clock signal source;
• and
• a plurality of first delay line output taps;
• a plurality of transmission gates each of which include:
• a first signal terminal coupled to one of the plurality of first delay line output taps;
• a second signal terminal coupled to a common output;
• and
• a gate control terminal;
• a plurality of decoders each of which includes:
• one or more decoder address inputs;
• and
• a plurality of decoder outputs;
• a plurality of gate signal delay lines each of which is characterized by one of a plurality of delay durations and includes:
• an input that is coupled a decoder output of each of the plurality of decoders;
• an output coupled to the gate control terminal of one of the plurality transmission gates.
• a controller including:
• a set of control signal outputs coupled to the one or more decoder address inputs of the plurality of decoders.

A method of digitally synthesizing a signal, the method comprising the steps of:

• generating a clock signal that includes a plurality of successive clock signal periods;
• coupling the clock signal to a delay line that includes:
• an input end;
• a plurality of taps including:
• a zeroth tap that is located closest to the input end;
• and
• a last tap that is furthest from the input end;
• and
• during at least one clock signal period, selecting and coupling two or more of the plurality of taps to an output.