Method for fabricating transistor in semiconductor device

Abstract

A method for fabricating a transistor in a semiconductor device can minimize short-channel effects (SCE), reverse short-channel effects (RSCE), gate induced drain leakage (GIDL), and off leakage of a transistor and can reduce production costs through fabricating the transistor through a simple process. The method comprises the steps of: forming a pad oxide layer on a silicon substrate wherein a field oxide layer has been formed, forming a nitride layer thereon, forming a gate conductor mask pattern on the nitride layer thereby patterning the nitride layer, forming a spacer at both sides of the nitride through blanket etching after forming a first insulating layer on the entire resultant structure, implanting impurities into the silicon substrate outside of the spacer thereby forming a source and drain region, forming an LDD implant in the silicon substrate outside of the nitride layer after removing the spacer through a wet etching process, performing a planarization through a chemical-mechanical polishing (CMP) process after forming a thick second insulating layer on the entire resultant structure, performing a channel threshold voltage implantation and a punch stop implantation in the silicon substrate after removing the nitride layer, performing a planarization through a CMP process after forming a gate insulating layer on an exposed part of the silicon substrate and forming a gate conductor thereon, forming a contact to connect the source and drain region with the gate conductor, stacking a conductor on the resultant structure, performing planarization through a CMP process, and performing a metal patterning to complete production of the transistor for a semiconductor device.

Dependencies are inferred from the claim text.