Method of forming a dual damascene structure

A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon, said method comprising:

• depositing a first hard mask layer over the dielectric layer;
• depositing a second hard mask layer on the first hard mask layer, wherein said second hard mask layer exhibits a high etch selectivity with respect to said dielectric layer;
• depositing a third hard mask layer on the second hard mask layer;
• and
• completing formation of the dual damascene structure including etching a metal wiring pattern and a via pattern in said dielectric layer and depositing a conductive material in said etched metal wiring pattern and via pattern.

A method of forming a dual damascene structure, said method comprising:

• providing a substrate having a first interconnect layer formed thereon, said first interconnect layer including a dielectric material formed between a plurality of conductive lines;
• forming a barrier dielectric layer over said first interconnect layer;
• forming a via dielectric layer over said barrier dielectric layer;
• forming a porous low dielectric constant layer over said via dielectric layer;
• depositing a first hard mask layer over said porous low dielectric constant layer, wherein said first hard mask is a silicon-containing material;
• depositing a second hard mask layer over said first hard mask layer, wherein said second hard mask layer exhibits a high etch selectivity to said via dielectric layer and said porous low k dielectric layer;
• depositing a third hard mask layer over said second hard mask layer, wherein said third hard mask layer is a silicon-containing material;
• forming a bottom antireflective coating over said third hard mask;
• forming a photoresist layer over said third hard mask layer;
• patterning said photoresist layer in accordance with a metal wiring pattern to expose selected portions of said organic antireflective coating;
• etching said organic antireflective layer and said third hard mask layer to transfer said metal wiring pattern from said photoresist layer to said organic antireflective coating and said third hard mask layer;
• etching said second hard mask layer to transfer said metal wiring pattern to said second hard mask layer and removing said photoresist and bottom antireflective layer;
• forming a second organic antireflective coating over said patterned second hard mask layer;
• forming a second photoresist layer over said second organic antireflective coating;
• patterning said second photoresist layer in accordance with a via pattern to expose selected portions of said second bottom antireflective coating;
• etching a via hole through said second organic antireflective coating, said third, second and first hard mask layer and at least into said porous low dielectric constant layer;
• removing said second photoresist layer and said second organic antireflective coating;
• etching said metal wiring pattern into said porous low dielectric constant layer and transfer said via pattern into said via dielectric layer;
• etching through said barrier dielectric layer in said via to expose portions of said first interconnect layer;
• and
• filling said etched via and metal wiring pattern with a conductive material.