Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics

A method of forming a transistor, comprising:

• forming first and second source/drain regions;
• forming a body region between the first and second source/drain regions;
• evaporation depositing a praseodymium (Pr) layer on the body region;
• oxidizing the Pr layer to form a Pr2O3 oxide layer on the body region;
• and
• coupling a gate to the Pr2O3 oxide layer.

A method of forming a memory array, comprising:

• forming a number of access transistors, comprising:
• forming first and second source/drain regions;
• forming a body region between the first and second source/drain regions;
• evaporation depositing a praseodymium (Pr) layer on the body region;
• oxidizing the Pr layer to form a Pr2O3 oxide layer on the body region;
• coupling a gate to the Pr2O3 oxide layer;
• forming a number of wordlines coupled to a number of the gates of the number of access transistors;
• forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.

A method of forming an information handling system, comprising:

• forming a processor;
• forming a memory array, comprising:
• forming a number of access transistors, comprising:
• forming first and second source/drain regions;
• forming a body region between the first and second source/drain regions;
• evaporation depositing a praseodymium (Pr) layer on the body region;
• oxidizing the Pr layer to form a Pr2O3 oxide layer on the body region;
• coupling a gate to the Pr2O3 oxide layer;
• forming a number of wordlines coupled to a number of the gates of the number of access transistors;
• forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors;
• and
• forming a system bus that couples the processor to the memory array.

A transistor, comprising:

• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a praseodymium oxide dielectric layer coupled to the surface portion of the body region;
• and
• a gate coupled to praseodymium oxide dielectric layer.

A memory array, comprising:

• a number of access transistors, comprising:
• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a praseodymium oxide dielectric layer coupled to the surface portion of the body region;
• a gate coupled to the praseodymium oxide dielectric layer;
• a number of wordlines coupled to a number of the gates of the number of access transistors;
• a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.

An information handling device, comprising:

• a processor;
• a memory array, comprising:
• a number of access transistors, comprising:
• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a praseodymium oxide dielectric layer coupled to the surface portion of the body region;
• a gate coupled to the praseodymium oxide dielectric layer;
• a number of wordlines coupled to a number of the gates of the number of access transistors;
• a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors;
• and
• a system bus coupling the processor to the memory device.

A transistor formed by the process, comprising:

• forming a body region coupled between a first source/drain region and a second source/drain region;
• evaporation depositing a praseodymium (Pr) metal layer on the body region;
• oxidizing the Pr metal layer to form a Pr2O3 oxide layer on the body region;
• and
• coupling a gate to the Pr2O3 oxide layer.

A transistor, comprising:

• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a Pr2O3 oxide dielectric layer coupled to the surface portion of the body region, wherein the oxide dielectric layer has a dielectric constant of about 31;
• and
• a gate coupled to Pr2O3 oxide dielectric layer.