Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors

A method for aligning a mask with prior formed structures in an active area of a circuit region when an alignment mark region is covered by an opaque material layer, the method comprising the steps of:

• forming an alignment mark structure in the alignment mark region using standard process steps for forming a vertical gate transistor, the forming alignment mark structure step comprising the steps of:
• forming a deep trench stud in an alignment mark region concurrently with a formation of a vertical gate transistor electrode in a circuit region,
• etching the stud to reduce a top area of the stud and forming an isolation trench in the alignment mark region adjacent to the stud, both concurrently with a formation of an isolation trench adjacent to the vertical gate transistor electrode in the circuit region,
• filling the alignment mark isolation trench with an insulating material while filling the circuit region isolation trenches with the insulating material, and
• removing a portion of the insulating material from the alignment mark isolation trench to a level below the top of the stud so that an upper portion of the stud extends above the insulating material, concurrently with a removal of a portion of the insulating material from the circuit region;
• forming the opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region;
• viewing the alignment mark structure through the mask, wherein a step feature formed by the stud is still present after the opaque material layer covers the alignment mark structure;
• and
• aligning an alignment mark portion of the mask with the alignment mark structure.

An alignment mark structure for aligning a mask with prior formed features of in a circuit region when an opaque material layer covers the alignment mark structure, comprising:

• an alignment mark region stud extending from a deep trench filled with gate material located in an alignment mark region, wherein the alignment mark region stud is formed concurrently with a formation of a circuit region stud for a vertical gate transistor in a circuit region and without requiring additional processing steps solely for the formation of the alignment mark region stud, and wherein the alignment mark region stud has a top area defined by an active area mask;
• an isolation trench formed adjacent to the deep trench filled with gate material in the alignment mark region, the alignment mark region isolation trench being filled with insulating material, wherein the alignment mark region isolation trench filled with the insulating material is formed concurrently with a formation of an isolation trench filled with the insulating material that is located adjacent to the vertical gate transistor in the circuit region, and without requiring additional processing steps solely for the formation of the alignment mark region isolation trench filled with the insulating material;
• and
• a step feature formed between the top of the insulating material in the alignment mark region isolation trench and the top of the alignment mark region stud, wherein the height of the step feature is large enough that the step feature remains visible after the opaque material layer covers the alignment mark structure.