Method for fabricating highly integrated transistor

Abstract

A method for fabricating a highly integrated transistor comprises the steps of forming a first conductive well region on a silicon substrate, forming an isolation oxide layer on the desired region of the entire surface of the silicon substrate, forming a first pad oxide layer on the entire surface of the silicon substrate, forming a second conductive LDD (low doped drain) region and a second source/drain region on an active region of the silicon substrate, and forming a pad nitride layer on the first oxide layer. Next, in the method for fabricating such a transistor, a trench is formed through sequential etching desired parts of the pad nitride layer, the first oxide layer, the source/drain region, and the LDD region; a second pad oxide layer is formed along the surfaces of the source/drain region and the LDD region having been exposed at the inside of the trench; and the LDD region and the upper part of the well region are removed after the removal of the second pad oxide layer formed at the bottom of the trench. Then, a gate is formed in the trench, an interlayer insulating layer is formed on the entire surface of the resultant structure, and the interlayer insulating layer is etched selectively to result in the production of a source electrode, a drain electrode, and a gate electrode, each of which is electrically connected with the source/drain region and the gate.

Dependencies are inferred from the claim text.