Methods of forming capacitor structures and DRAM arrays

A method of forming a capacitor comprising the following steps:

• forming a first layer over a node location;
• forming a semiconductive material masking layer over the first layer;
• etching an opening through the semiconductive material masking layer and the first layer to the node location using the semiconductive material masking layer as an etch mask;
• forming a storage node layer to substantially fill the opening and be in electrical connection with the masking layer;
• removing portions of the masking layer and the storage node layer to form a capacitor storage node comprising the masking layer and the storage node layer;
• forming a capacitor dielectric layer operatively proximate the capacitor storage node;
• and
• forming an outer capacitor plate operatively proximate the capacitor dielectric layer.

A method of forming a capacitor comprising the following steps:

• forming a storage node which in lateral cross-section comprises an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and a pair of laterally opposing cavities beneath the storage node;
• forming a dielectric layer against the storage node outer surface;
• and
• forming a cell plate layer against the dielectric layer.

A method of forming a capacitor storage node comprising the following steps:

• forming a first layer over a node location;
• forming a semiconductive material masking layer over a portion of the first layer to form a masked portion and an unmasked portion of the first layer;
• removing the unmasked portion of the first layer to form an opening to the node location;
• and
• forming an electrical connection from the node location to the semiconductive material masking layer to form a capacitor storage node comprising the semiconductive material masking layer.

A method of forming a DRAM cell comprising the following steps:

• forming a storage node which in lateral cross-section comprises an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node;
• forming a dielectric layer against the storage node outer surface;
• forming a cell plate layer against the dielectric layer;
• the storage node, dielectric layer and cell plate layer being together configured to form a capacitor;
• forming a bitline;
• and
• forming a transistor gate to electrically connect the bitline to the capacitor.

A method of forming a DRAM array comprising the following steps:

• defining a first node location, a second node location, and a third node location on a semiconductor substrate;
• forming a first transistor gate to electrically connect the first and second node locations;
• forming a second transistor gate to electrically connect the second and third node locations;
• forming a first layer of electrically insulative material over the first, second and third node locations;
• forming a patterned undoped polysilicon masking layer over the first layer of insulative material, the patterned undoped polysilicon masking layer forming unmasked portions of the first layer of insulative material over the first, second and third node locations, and masked portions of the first layer of insulative material between the unmasked portions;
• removing the unmasked portions of the first layer of insulative material to form first, second and third openings, and to expose the first, second and third node locations within the respective first, second and third openings;
• forming a doped polysilicon layer within the first, second and third openings and in electrical contact with the first, second and third node locations, the formed doped polysilicon layer extending over the patterned polysilicon masking layer;
• removing a portion of the doped polysilicon layer from over the second node location to form an electrically isolated pedestal from the doped polysilicon in contact with the second node location and to form first and second capacitor storage nodes from the doped polysilicon in contact with the first and third node locations, respectively;
• the first and second storage nodes comprising portions of the undoped polysilicon masking layer;
• doping the portions of the undoped polysilicon masking layer comprised in the storage nodes by out-diffusion of dopant from the doped polysilicon layer comprised in the storage nodes;
• roughening an outermost surface of the doped polysilicon layer, the roughening comprising forming a rugged polysilicon layer over the doped polysilicon and removing the rugged polysilicon from between the pedestal and the first and second capacitor storage nodes to electrically isolate the pedestal from the first and second capacitor storage nodes;
• forming a dielectric layer and a cell plate layer over the roughened outermost surface of the doped polysilicon;
• the dielectric layer, cell plate layer and respective first and second capacitor storage nodes together forming respective first and second capacitors;
• removing the dielectric layer and cell plate layer from between the pedestal and the first and second capacitor storage nodes;
• forming a second layer of electrically insulative material over the pedestal and over the first and second capacitors;
• removing a portion of the second layer of electrically insulative material from over the pedestal to form a bitline plug opening and to expose an electrically conductive surface of the pedestal;
• forming a bitline plug within the bitline plug opening and in physical contact with the exposed electrically conductive surface of the pedestal;
• and
• forming a conductive bitline over the first and second capacitors, the bitline electrically contacting the second node location through the bitline plug and the pedestal.

A method of forming a monolithic integrated circuit comprising the following steps:

• fabricating integrated circuitry over a portion of a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements;
• the fabrication of at least one of the capacitors comprising the following steps:
• forming a first layer over a node location;
• forming a semiconductive material masking layer over the first layer;
• etching an opening through the semiconductive material masking layer and the first layer to the node location using the semiconductive material masking layer as an etch mask;
• forming a storage node layer within the opening and in electrical connection with the masking layer;
• removing at least a portion of the masking layer to form a capacitor storage node comprising the masking layer and the storage node layer;
• forming a capacitor dielectric layer operatively proximate the capacitor storage node;
• and
• forming an outer capacitor plate operatively proximate the capacitor dielectric layer.

A DRAM -cell comprising:

• a capacitor comprising:
• a storage node comprising a top and in lateral cross-section comprising a pair of opposing lateral surfaces;
• an insulative layer beneath the storage node;
• laterally opposing cavities between the storage node and the insulative layer;
• the storage node in lateral cross-section comprising an outer surface extending over the top of the storage node, along the pair of opposing lateral surfaces of the storage node, and within the laterally opposing cavities beneath the storage node;
• a dielectric layer against the storage node outer surface;
• a cell plate layer against- the dielectric layer;
• a bitline;
• and
• a transistor gate electrically connecting the bitline to the capacitor.

A DRAM cell comprising:

• a capacitor comprising:
• a storage node comprising a polysilicon masking layer against a conductively doped polysilicon layer;
• a dielectric layer against the storage node;
• a cell plate layer against the dielectric layer;
• a bitline;
• and:
• a transistor gate electrically connecting the bitline to the capacitor.

A DRAM array comprising:

• a bitline node, a first capacitor node and a second capacitor node;
• the first capacitor node being electrically connected to the bitline node through a first transistor gate;
• the second capacitor node being electrically connected to the bitline node through a second transistor gate;
• a first capacitor electrically connected to the first capacitor node, and a second capacitor electrically connected to the second capacitor node, the first and second capacitors individually comprising:
• a storage node comprising a top and in lateral cross-section comprising a pair of opposing lateral surfaces;
• an insulative layer beneath the storage node;
• laterally opposing cavities between the storage node and the insulative layer;
• the storage node in lateral cross-section comprising an outer surface extending over the top of the storage node, along the pair of opposing lateral surfaces of the storage node, and within the laterally opposing cavities beneath the storage node;
• a dielectric layer against the storage node outer surface and extending along the lateral opposing surfaces of the storage node and within the opposing cavities beneath the storage node;
• and
• a cell plate layer against the dielectric layer and extending along the lateral opposing surfaces of the storage node and within the opposing cavities beneath the storage node;
• and
• a bitline electrically connected to the bitline node and extending over the first and second capacitors.

A monolithic integrated circuit comprising:

• fabricated circuitry over a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements;
• at least one of the capacitors comprising:
• a storage node comprising a top and in lateral cross-section comprising a pair of opposing lateral surfaces;
• an insulative layer beneath the storage node;
• laterally opposing cavities between the storage node and the insulative layer;
• the storage node in lateral cross-section comprising an outer surface extending over the top of the storage node, along the pair of opposing lateral surfaces of the storage node, and within the laterally opposing cavities beneath the storage node;
• a dielectric layer against the storage node outer surface;
• and
• a cell plate layer against the dielectric layer.