High speed differential data sampling circuit
OwnerJames Chow, Khin Lay +1inventors
InventorsJames Chow, Khin Lay, Kenny D. Wen
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Abstract
A differential data sampling circuit is provided for sampling an input signal line with precise timing so as to provide reduced sensitivity to noise. The differential data sampling circuit includes a latch circuit for initially sampling a differential data signal in response to a first strobe signal. The latch circuit operates to rapidly capture the signal level present on the input signal line. The output of the latch circuit is then sampled by a strobe circuit in order to capture and hold the output of the latch circuit based on a second strobe signal. In preferred embodiments, the latch circuit has a high input impedance. A digital data receiver including such a differential data sampling circuit is also provided.
Claims20
A differential data sampling circuit comprising:
- a latch circuit for sampling a differential data signal in response to a first strobe signal;
- and
- a strobe circuit coupled to the latch circuit, the strobe circuit capturing the output of the latch circuit based on a second strobe signal.
A digital data receiver including at least one differential data sampling circuit, said differential data sampling circuit comprising:
- a latch circuit for sampling a differential data signal in response to a first strobe signal;
- and
- a strobe circuit coupled to the latch circuit, the strobe circuit capturing the output of the latch circuit based on a second strobe signal.
Dependencies are inferred from the claim text.