Spread spectrum clocking tolerant receivers
AssigneeIntel Corporation
InventorHarry G. Skinner
Life of this patent
Estimating the term…
Abstract
In some embodiments, the invention includes a system having a clock recovery circuitry to receive a data signal and a reference clock signal and in response thereto to produce an in phase clock signal which is in phase with the data signal and mirrors frequency changes in the data signal, wherein the data signal has embedded clock information and a varying frequency. The system also includes a receiving gate to receive the data signal and the in phase clock signal and to gate the data signal to produce a gated data signal in response to the in phase clock signal. Other embodiments are described and claimed.
Claims26
A system comprising:
- clock recovery circuitry to receive a data signal and a reference clock signal and in response thereto to produce an in phase clock signal which is in phase with the data signal and mirrors frequency changes in the data signal, wherein the data signal has embedded clock information and a varying frequency;
- and
- a receiving gate to receive the data signal and the in phase clock signal and to gate the data signal to produce a gated data signal in response to the in phase clock signal.
A system comprising:
- a receiving gate to receive a data signal and an in phase clock signal and to gate the data signal to produce a gated data signal in response to the in phase clock signal, wherein the data signal has embedded clock information and a varying frequency;
- and
- clock recovery circuitry to receive the gated data signal and a reference clock signal and in response thereto to produce the in phase clock signal which is in phase with the data signal and mirrors frequency changes in the data signal.
A system comprising:
- clock recovery circuitry to receive a data signal and in response thereto to produce an in phase clock signal which is in phase with the data signal and mirrors frequency changes in the data signal, wherein the data signal has embedded clock information and a varying frequency;
- and
- a receiving gate to receive the data signal and the in phase clock signal and to gate the data signal to produce a gated data signal in response to the in phase clock signal.
A system comprising:
- a receiving gate to receive a data signal and an in phase clock signal and to gate the data signal to produce a gated data signal in response to the in phase clock signal, wherein the data signal has embedded clock information and a varying frequency;
- and
- clock recovery circuitry to receive the gated data signal and in response thereto to produce the in phase clock signal which is in phase with the data signal and mirrors frequency changes in the data signal.
Dependencies are inferred from the claim text.