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US 2003/0118050 A1Published application
Method and apparatus for vector based sequence generation
AssigneeTexas Instruments Incorporated
InventorsJohn G. McDonough, Douglas R. Walby, Karim Abdulla
Life of this patent
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Abstract
A vector-based sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The sequence generator (100) can also produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.
Claims17
A vector based sequence generator providing an N-bit output sequence from a Y-bit length sequence, comprising:
- an input port for receiving an X-bit length index signal used for selecting the desired starting bit location in the Y-bit length sequence;
- at least first and second storage areas coupled to the input port;
- and
- an output sequence ordering function circuit coupled to the at least first and second storage areas, the output sequence ordering function circuit having an output port for providing the N-bit output;
- and
- some of the bits from the X-bit length index signal are used to address the at least two storage areas, and some other bits from the X-bit length index signal are used to configure the output sequence ordering function circuit in order to select the bit order for the N-bit output.
3 more elements
A method for vector based sequence generation providing an N-bit output from a Y-bit length sequence, comprising the steps of:
- a) receiving an index value having a predetermined number of bits;
- b) using the index value to select the desired starting bit location in the Y-bit length sequence;
- c) using some of the bits of the index value to address at least two different storage areas;
- d) using some of the bits of the index value other than those used in step c) in order to control where the outputs of the at least two different storage areas are directed;
- and
- e) using some of the bits of the index value other than those used in steps c) and d) to control an output sequence ordering function that provides the N-bit output.
3 more elements
Dependencies are inferred from the claim text.