Reconfigurable data packet header processor
AssigneeChip Engines
InventorsParitosh Kulkarni, Nirmal Raj Saxena
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AssigneeChip Engines
InventorsParitosh Kulkarni, Nirmal Raj Saxena
Estimating the term…
The present invention addresses the need for improved network data handling with a flexible, single point solution for packet header processing of data packets in a variable format transfer environment without associated performance or rate degradation. The present invention introduces a programmable or reconfigurable data packet header processor, wherein various registers (50, 55 and 60) of a chip are selectively programmed with a set of values that map the length (48) and location (44) of various header fields (20, 23, 25) to their position measured from the start of the packet (29). Unlike dedicated hardware solutions, these updateable registers are designed to store length (48), position (44) and type (40) data relating to multiple packet formats to improve extraction of packet header information by guiding the extraction to the exact point of the desired field information.
A device for improving packetized data routing, comprising the following:
A method for improving network data packet handling comprising the steps of:
A device for improved data header extraction, comprising the following:
Dependencies are inferred from the claim text.