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US 2003/0117933 A1Published application
Low clock swing latch for dual-supply voltage design
AssigneeIntel Corporation
InventorsSteven K. Hsu, Bhaskar P. Chatterjee, Ram K. Krishnamurthy
Life of this patent
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Abstract
A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.
Claims27
A latch comprising:
- an input circuit including a first and a second input switch connected together at a pulldown node, and a pulldown device connected between the pulldown node and a reference node;
- a pullup circuit connected to the first input switch at a first internal node and to the second input switch at a second internal node;
- and
- a feedback circuit including a first feedback switch connected to the first internal node and a second feedback switch connected to the second internal node, and an isolation device connected between the reference node and a node common to the first and second feedback switches.
1 more element
A latch comprising:
- a first input transistor connected between a first internal node and a pulldown node;
- a second input transistor connected between a second internal node and the pulldown node, and an input inverter connected between a gate of the first input transistor and a gate of the second input transistor;
- a pulldown transistor connected between the pulldown node and a reference node;
- a first pullup transistor connected between the first internal node and a first supply node;
- a second pullup transistor connected between the second internal node and the first supply node;
- and
- a feedback circuit including a first feedback transistor connected between the first internal node and a common node, a second feedback transistor connected between the second internal node and the common node, and a third feedback transistor connected between the common node the reference node.
4 more elements
A latch comprising:
- a clock path including a first and a second clock node to provide complementary clock signals;
- a data path to receive a data signal, the data path including a first and a second input switch connected together at a pulldown node, and a pulldown device connected between the pulldown node and a reference node;
- a pullup circuit connected to the first input switch at a first internal node and to the second input switch at a second internal node;
- and
- a feedback circuit including a first stack of transistors connected to the first and second clock nodes and connected between the first and second internal nodes, and a second stack of transistors connected to the first and second clock nodes and connected between the first and second internal nodes.
2 more elements
An integrated circuit comprising:
- a first functional unit to output a data signal;
- and
- a latch connected to the first functional unit, the latch including:
- a clock path to receive a clock signal, the clock path being connected to a pulldown device;
- a data path to receive the data signal to produce an output signal at an output node, the data path including a first transistor connected between a first internal node and the pulldown device, a second transistor connected between a second internal node and the pulldown device, and an inverter connected between one of the internal nodes and the output node;
- a pullup circuit connected between a supply node and the first and second internal nodes;
- and
- a feedback circuit including a first feedback transistor connected between the first internal node and a common node, a second feedback transistor connected between the second internal node and the common node, and a third feedback transistor connected to the common node and the clock path.
5 more elements
Dependencies are inferred from the claim text.