Address decoder
OwnerYoshihiro Hori, Toshitaka Kumainventors
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Abstract
An address decoder includes a PLL circuit generating a PLL clock signal synchronized with an external clock signal, a frequency divider dividing the PLL clock signal, a selector selecting a binary wobble signal or an inverted signal thereof, a timing generator generating each of sync window signals, a biphase enable signal, CRC enable signals, a CRC polarity signal, and an output enable signal, a biphase decoder decoding a wobble signal selected by the selector, a Gray code decoder decoding a biphase decode data, and an output control circuit outputting a decoded address signal. Therefore, this address decoder can reproduce an address signal by decoding the wobble signal.
Claims6
An address decoder to reproduce an address signal based on a wobble signal detected from an optical disk having a land and a groove and having an address preformatted therein by forming a wobble on the groove, comprising:
- biphase decoding means decoding said wobble signal and outputting a biphase error signal indicating a presence or absence of a generation of a biphase error upon said decoding;
- Gray code decoding means decoding a signal output from said biphase decoding means;
- and
- an output control means controlling an output of a signal output from said Gray code decoding means as an address signal based on said biphase error signal
Dependencies are inferred from the claim text.