Fast cycle RAM and data readout method therefor
AssigneeKabushiki Kaisha Toshiba
InventorsShigeo Ohshima, Nobuo Watanabe
Life of this patent
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Abstract
A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.
Claims14
A semiconductor memory device in which first and second commands are input to effect a read/write operation of random data with respect to a memory cell array in synchronism with a clock signal and a row access command and a column access command for data readout are supplied as one packet in two successive clock cycles, comprising:
- a first pin supplied with a signal for distinguishing a read command and a write command;
- second pins supplied with upper-side and lower-side decode addresses;
- a controller to which a signal indicating that the read command is input and a signal indicating that the write command is input based on the signal input to said first pin are supplied;
- a first command decoder controlled by an output signal of said controller, for defining the readout/ write operation by use of the first command, fetching an upper-side decode address of a memory cell array via said second pin and decoding the first command;
- and
- a lower-side command decoder controlled by an output signal of said controller, for fetching a lower-side decode address of the memory cell array via the control pin in response to the second command and decoding the lower-side command.
A data readout method for a semiconductor memory device in which a row access command and a column access command for data readout are supplied as one packet in two successive clock cycles, comprising:
- a first step of inputting a first command in response to a change of a clock signal to define one of readout and write operations and fetching an upper-side decode address of a memory cell array to operate a row-series peripheral circuit, select a word line and drive a sense amplifier;
- and
- a second step of inputting a second command in response to a change of the clock signal one clock cycle after the present cycle to fetch a lower-side decode address of the memory cell array, release selection of the word line and transfer data.
A data readout method for a semiconductor memory device in which first and second commands are input to effect a random data readout/write operation with respect to a memory cell array in synchronism with a clock signal and a row access command and a column access command for data readout are supplied as one packet in two successive clock cycles, comprising the steps of:
- defining one of readout and write operations and fetching an upper-side decode address of the memory cell array in response to the first command;
- and
- fetching a lower-side decode address of the memory cell array in response to the second command.
A data readout method for a semiconductor memory device in which first and second commands are input to effect a random data readout/write operation with respect to a memory cell array in synchronism with a clock signal, comprising the steps of:
- fetching a row address in response to input of the first command next to a standby state;
- and
- directly supplying a read command (Read with Auto-close) instead of a row access command for starting the operation of a peripheral row-series circuit.
A data readout method for a semiconductor memory device in which first and second commands are input to effect a random data readout/write operation with respect to a memory cell array in synchronism with a clock signal, comprising the steps of:
- fetching a row address in response to input of the first command next to a standby state;
- and
- directly supplying a write command (Write with Auto-close) instead of a row access command for starting the operation of a peripheral row-series circuit.
Dependencies are inferred from the claim text.