Non-volatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsHitoshi Shiga, Tokumasa Hara, Tadayuki Taura
Life of this patent
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Abstract
A non-volatile semiconductor memory device comprises a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time, a sense amplifier, and an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
Claims11
A non-volatile semiconductor memory device comprising:
- a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time;
- a sense amplifier;
- and
- an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
A non-volatile semiconductor memory device comprising:
- a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time;
- a sense amplifier;
- and
- an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells in a predetermined number of blocks after pre-programming, the predetermined number of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
A method for executing an erase sequence on a non-volatile semiconductor memory device including a plurality of blocks each having a plurality of memory cells, comprising:
- confirming erase execution of a first block to be pre-programmed and then pre-programming the first block;
- confirming erase execution of a next block and then pre-programming the next block;
- similarly confirming erase execution of further next blocks one by one and then pre-programming the further next blocks one by one;
- and
- then, executing collective erase for each of the blocks.
Dependencies are inferred from the claim text.