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US 2003/0117882 A1Published application
Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorTae Yun Kim
Life of this patent
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Abstract
A semiconductor memory device that generates, during a test operation, a burst control signal having a short pulse in a disable time of a burst control signal by using a pulse generator to control a precharge time. Accordingly, the semiconductor memory device, when receiving a high frequency operation clock signal, can be tested without delay of a test time by using a test circuit operated synchronously with a low frequency operation clock signal.
Claims6
A semiconductor memory device, comprising:
- a state control unit configured to receive external control signals and output internal commands;
- a burst length control unit configured to receive the internal commands from the state control unit and output a burst control signal for maintaining an active state of a column operation for as long as a burst length;
- a clock buffer configured to receive an external clock signal and generate a pulse clock signal for generating a pulse in accordance with a rising edge of the external clock signal and an inverted clock signal having a phase opposite to a phase of the external clock signal;
- a burst control signal generating unit configured to receive the burst control signal from the burst length control unit and generate an inverted burst control signal having a phase opposite to a phase of the burst control signal and a test mode burst control signal having a short pulse occurring within a disable time of the burst control signal;
- a burst end control unit that is controlled according to a test mode signal indicating a test mode, the burst end control unit configured to generate a burst end signal indicating a burst end time, by being synchronized with the inverted clock signal and using the inverted burst control signal during a normal operation, and by being synchronized with the pulse clock signal and using the test mode burst control signal during a test operation;
- and
- a precharge control unit configured to perform a precharge operation according to the burst end signal.
4 more elements
Dependencies are inferred from the claim text.