Multi-mode synchronouos memory device and method of operating and testing same

A synchronous semiconductor device selectively operable in a normal mode of operation and an alternative mode of operation, comprising:

• a first input terminal for receiving a first asynchronous input signal;
• a second input terminal for receiving a second asynchronous input signal;
• a command bus for receiving a plurality of synchronous control signals;
• a clock terminal for receiving an external clock signal;
• an clocking circuit, coupled to said clock terminal, said clocking circuit being responsive to said clock signal to generate at least one internal clock signal;
• wherein said device is responsive to assertion of said first asynchronous signal while said second asynchronous signal is deasserted to perform a first function in said normal mode of operation and is responsive to assertion of said second asynchronous signal while said first asynchronous signal is deasserted to perform a second function in said normal mode of operation;
• and wherein said device is responsive to concurrent assertion of said first and second asynchronous signals to enter into said alternative mode of operation.

A method of operating a synchronous semiconductor device operable in a normal mode of operation and an alternative mode of operation, comprising:

• (a) responding to assertion of a first asynchronous input signal and deassertion of a second asynchronous signal to perform a first function in said normal mode of operation;
• (b) responding to assertion of said second asynchronous signal and deassertion of said first asynchronous signal to perform a second function in said normal mode of operation;
• and
• (c) responding to concurrent assertion of said first and second asynchronous signals to enter into said alternative mode of operation.

A method of testing a synchronous semiconductor device having both synchronously and asynchronously captured input terminals and a clock input terminal, and specified to operate in a normal mode at no less than a minimum synchronous clock frequency, comprising:

• (a) applying a predetermined sequence of asynchronous input signals to said asynchronous input terminals to initialize said device into a testing mode;
• (b) in response to initialization into said testing mode, disabling an internal clocking circuit in said device;
• (c) applying a clock signal having a frequency less than said minimum synchronous clock frequency to said clock input terminal;
• and
• (d) testing operation of the device operating in said testing mode.

A synchronous dynamic random access memory device operable in a normal mode of operation and a testing mode of operation, comprising:

• a plurality of synchronously captured input signal terminals;
• at least two asynchronously captured input signal terminals;
• a synchronous clock terminal for receiving an external clock signal;
• an internal clocking circuit coupled to the synchronous clock terminal and responsive to said external clock signal to generate at least one internal clock signal;
• control circuitry coupled to said plurality of synchronously captured input signal terminals and to said at least two asynchronously captured input signal terminals;
• wherein said memory device is specified to operate in normal mode using an external clock signal having a frequency above a predetermined minimum normal operating frequency;
• and wherein said control circuitry is responsive to a predetermined sequence of asynchronous input signals applied to said at least two asynchronously captured input signal terminals to disable said internal clocking circuit and thereafter operate said memory device in said testing mode of operation;
• and wherein said external clock signal during operation in said testing mode of operation has a frequency less than said predetermined minimum normal operating frequency.

A memory module, comprising a plurality of discrete semiconductor memory devices mounted on a printed circuit board, wherein each of said plurality of discrete semiconductor memory devices is operable in a normal mode of operation and an alternative mode of operation, each discrete semiconductor memory device comprising:

• a first input terminal for receiving a first asynchronous input signal;
• a second input terminal for receiving a second asynchronous input signal;
• a command bus for receiving a plurality of synchronous control signals;
• a clock terminal for receiving an external clock signal;
• an clocking circuit, coupled to said clock terminal, said clocking circuit being responsive to said clock signal to generate at least one internal clock signal;
• wherein said device is responsive to assertion of said first asynchronous signal while said second asynchronous signal is deasserted to perform a first function in said normal mode of operation and is responsive to assertion of said second asynchronous signal while said first asynchronous signal is deasserted to perform a second function in said normal mode of operation;
• and wherein said device is responsive to concurrent assertion of said first and second asynchronous signals to enter into said alternative mode of operation.