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US 2003/0117880 A1Published application
Pseudo-static single-ended cache cell
AssigneeIntel Corporation
InventorsSteven K. Hsu, Ram Krishnamurthy
Life of this patent
Estimating the term…
Abstract
A cache memory cell comprising a read-access transistor to access the cell, where the read-access transistor is reverse biased when the memory cell is not being read to reduce sub-threshold leakage current.
Claims23
A memory comprising:
- a local bit line;
- and
- a memory cell comprising:
- a read port;
- a read-access transistor having a first source/drain connected to the local bit line, and having a second source/drain and a gate;
- and
- a NAND gate having an output port connected to the second source/drain of the read-access transistor and having a first input port connected to the read port.
4 more elements
A memory having an evaluation phase and a pre-charge phase, the memory comprising:
- a local bit line;
- and
- a memory cell to store a logical state, the memory cell comprising:
- a read-access transistor to conditionally discharge the local bit line during a read operation on the memory cell depending upon the stored logical state, the read-access transistor having a source and a gate, wherein the gate of the read-access transistor is held LOW during a pre-charge phase, and wherein during an evaluation phase the gate of the read-access transistor is held HIGH only if a read operation is performed on the memory cell;
- and
- wherein the read-access transistor is reverse biased if the gate of the read-access transistor is LOW and the local bit line is HIGH.
3 more elements
A memory cell comprising:
- a read port;
- a read-access transistor having a source/drain and a gate;
- and
- a NAND gate having an output port connected to the source/drain of the read-access transistor and having a first input port connected to the read port.
1 more element
A memory having a pre-charge phase and an evaluation phase, the memory comprising:
- a local bit line;
- a pullup transistor to charge or maintain the local bit line HIGH during a pre-charge phase;
- and
- a memory cell comprising:
- a read port having a dynamic read select signal, wherein the dynamic read select signal is LOW during a pre-charge phase, and is HIGH during an evaluation phase only if a read operation is performed on the memory cell;
- a static circuit to store a logical state;
- and
- a read-access transistor to conditionally discharge the local bit line during a read operation on the memory cell depending upon the stored logical state;
- wherein the read-access transistor is reverse biased if the dynamic read select signal is LOW and the local bit line is HIGH.
6 more elements
A memory comprising:
- a local bit line;
- a memory cell comprising:
- a read port having a dynamic read select signal;
- a static circuit to store a logical state;
- and
- a read-access transistor to conditionally discharge the local bit line only if the dynamic select signal is HIGH depending upon the stored logical state;
- the read-access transistor having a gate and a source/drain;
- and
- a NAND gate to drive the source/drain of the read-access transistor HIGH if the dynamic read-select signal is LOW.
6 more elements
A memory having an evaluation phase and a pre-charge phase, the memory comprising:
- a local bit line;
- and
- a memory cell to store a logical state, the memory cell comprising:
- a read-access transistor to conditionally discharge the local bit line during a read operation on the memory cell depending upon the stored logical state, the read-access transistor having a source and a gate, wherein the gate of the read-access transistor is held LOW during a pre-charge phase, and wherein during an evaluation phase the gate of the read-access transistor is held HIGH only if a read operation is performed on the memory cell;
- and
- wherein the read-access transistor has a zero drain-to-source voltage if the gate of the read-access transistor is LOW and the local bit line is HIGH.
3 more elements
A memory having a pre-charge phase and an evaluation phase, the memory comprising:
- a local bit line;
- a pullup transistor to charge or maintain the local bit line HIGH during a pre-charge phase;
- and
- a memory cell comprising:
- a read port having a dynamic read select signal, wherein the dynamic read select signal is LOW during a pre-charge phase, and is HIGH during an evaluation phase only if a read operation is performed on the memory cell;
- a static circuit to store a logical state;
- and
- a read-access transistor to conditionally discharge the local bit line during a read operation on the memory cell depending upon the stored logical state;
- wherein the read-access transistor has a zero drain-to-source voltage if the dynamic read select signal is LOW and the local bit line is HIGH.
6 more elements
Dependencies are inferred from the claim text.