Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device
AssigneeFujitsu Limited
InventorYuji Nakagawa
Life of this patent
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Abstract
A semiconductor memory device that reduces the time for conducting a multiple word line selection test and operates stably. The semiconductor memory device includes memory cell blocks, row decoders, sense amps, block control circuits, and sense amp drive circuits. Each block control circuit generates a reset signal. The reset signal is used to select the word lines with the row decoders at timings that differ between the blocks. Each block control circuit provides the reset signal to the associated row decoder. The block control circuit also provides the reset signal to the associated sense amp drive circuit so that the sense amps are inactivated at timings that differ between the blocks.
Claims13
A semiconductor memory device comprising:
- a plurality of memory cell blocks, wherein each of the memory cell blocks includes a plurality of memory cells and a plurality of word lines connected to the memory cells;
- a plurality of row decoders connected to the plurality of memory cell blocks, wherein each of the row decoders selects one of the word lines in an associated one of the memory cell blocks;
- a plurality of sense amp groups connected to the plurality of row decoders, wherein each of the sense amp groups amplifies cell information read from the plurality of memory cells of an associated one of the memory cell blocks;
- a plurality of block control circuits connected to the plurality of memory cell blocks, wherein each of the block control circuits simultaneously selects multiple word lines in an associated one of the memory cell blocks and generates a sense amp control signal;
- and
- a plurality of sense amp drive circuits connected to the plurality of block control circuits and the plurality of sense amp groups, wherein each of the sense amp drive circuits selectively activates an associated one of the sense amp groups based on the sense amp control signal of the associated one of the block control circuits;
- wherein each of the block control circuits generates at least one reset signal and provides the reset signal to an associated one of the row decoders and to an associated one of the sense amp drive circuits, the reset signal being provided to the associated one of the row decoders so that the timing for selecting the word lines with the row decoders differs between each block, and the reset signal being provided to the associated one of the sense amp drive circuits so that inactivation of the plurality of sense amp groups differs between each block.
The device according to claim G, wherein each of the sense amp drive circuits includes a latch circuit.
A method for conducting a multiple word line selection test on a semiconductor memory device provided with a plurality of memory cell blocks, which include a first memory cell block and a second memory cell block, each of the memory cell blocks having a plurality of memory cells and a plurality of word lines connected to the memory cells, and a plurality of sense amp groups connected to the first and second memory cell blocks, each of the sense amp groups amplifying cell information read from the plurality of memory cells of an associated one of the memory cell blocks, the method comprising:
- a first step for activating one of the plurality of word lines in the first memory cell block and activating the sense amp group associated with the first memory cell block after a predetermined time;
- a second step for activating word lines other than the one that has been activated in the first memory cell block;
- a third step for activating one of the plurality of word lines in the second memory cell block and activating the sense amp group associated with the second memory cell block after a predetermined time;
- and
- a fourth step for activating word lines other than the one that has been activated in the second memory cell block;
- wherein the third and fourth steps are performed while the first and second steps are continuously performed or the second and fourth steps are performed while the first and third steps are continuously performed.
A method for conducting a multiple word line selection test on a semiconductor memory device provided with a plurality of memory cell blocks, which include a first memory cell block and a second memory cell block, each of the memory cell blocks having a plurality of memory cells and a plurality of word lines connected to the memory cells, and a plurality of sense amp groups connected to the first and second memory cell blocks, each of the sense amp groups amplifying cell information read from the plurality of memory cells of an associated one of the memory cell blocks, the method comprising:
- a first step for inactivating multiple word lines in the first memory cell block and the sense amp group associated with the first memory cell block;
- and
- a second step for inactivating multiple word lines in the second memory cell block and the sense amp group associated with the second memory cell block after performing the first step.
A method for conducting a multiple word line selection test on a semiconductor memory device provided with a plurality of memory cell blocks, which include a first memory cell block and a second memory cell block, each of the memory cell blocks having a plurality of memory cells and a plurality of word lines connected to the memory cells, and a plurality of sense amp groups connected to the first and second memory cell blocks, each of the sense amp groups amplifying cell information read from the plurality of memory cells of an associated one of the memory cell blocks, the method comprising:
- a first step for activating one of the plurality of word lines in the first memory cell block and activating the sense amp group associated with the first memory cell block after a predetermined time;
- a second step for activating word lines other than the one that has been activated in the first memory cell block;
- a third step for activating one of the plurality of word lines in the second memory cell block and activating the sense amp group associated with the second memory cell block after a predetermined time;
- a fourth step for activating word lines other than the one that has been activated in the second memory cell block;
- a fifth step for inactivating multiple word lines in the first memory cell block and the sense amp group associated with the first memory cell block;
- and
- a sixth step for inactivating multiple word lines in the second memory block and the sense amp group associated with the second memory block after performing the fifth step;
- wherein the third and fourth steps are performed while the first and second steps are continuously performed or the second and fourth steps are performed while the first and third steps are continuously performed.
A semiconductor memory device comprising:
- a plurality of memory cell blocks, wherein each of the memory cell blocks includes a plurality of memory cells and a plurality of word lines connected to the memory cells;
- a plurality of row decoders connected to the plurality of memory cell blocks, wherein each of the row decoders selects one of the word lines in an associated one of the memory cell blocks;
- a plurality of sense amp groups connected to the plurality of memory cell blocks, wherein each of the sense amp groups amplifies cell information read from the plurality of memory cells of an associated one of the memory cell blocks;
- a plurality of block control circuits connected to the plurality of row decoders, wherein each of the block control circuits simultaneously selects multiple word lines in an associated one of the memory cell blocks and generates a sense amp control signal;
- and
- a plurality of sense amp drive circuits connected to the plurality of block control circuits and the plurality of sense amp groups, wherein each of the sense amp drive circuits selectively activates an associated one of the sense amp groups based on the sense amp control signal of the associated one of the block control circuits, each of the sense amp drive circuits including a latch circuit.
Dependencies are inferred from the claim text.