Semiconductor memory and method for bit and/or byte write operation
OwnerTakashi Yamadainventor
Life of this patent
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Abstract
A semiconductor memory is disclosed that may provide bit and/or byte write functionalities with smaller increase in area, reduced power consumption and reduction in design time. According to one embodiment, a semiconductor memory may include a number of banks that each includes memory cell arrays (A00 to Anm), a column selector (C00 to Cnm), a sense amplifier/write driver section (R00 to Rnm), and a data input/output section (I00 to I0n). In a bit (or byte) write mode, an input/output section can disable a write to a bit (or byte) by driving a bit lines to a same potential as a precharge operation, regardless of the fact that a memory cell has been connected to such bit lines by a word line and column selector.
Claims20
A semiconductor memory, comprising:
- a plurality of circuit blocks, each associated with at least one access bit of a plurality of access bits, each circuit block including,
- a memory cell array having a plurality of memory cells selectable by word lines and bit lines,
- a sense amplifier/write driver section, and
- a column selector that selects at least one bit line pair according to a column address;
- and
- an input/output (I/O) section associated with each of the plurality of access bits, in a write disable mode, each I/O section driving both lines of a bit line pair selected by the column address to a same potential.
A method of selectively writing bit data to a semiconductor memory device, comprising the steps of:
- in a write enable mode, driving a bit line pair selected according to at least a portion of a memory address with complementary data values;
- and
- in a write disable mode, driving both lines of a bit line pair selected according to at least a portion of a memory address to a same potential.
A semiconductor memory, comprising:
- a plurality of memory cells selectable according to memory addresses;
- and
- a plurality of input/output (I/O) sections, each associated with a data line pair, each I/O section driving both lines of the associated data line pair to the same potential while a memory cell is coupled to the data line pair in response to an inactive bit write enable signal.
Dependencies are inferred from the claim text.