US 2003/0117874 A1 · Semiconductor memory device capable of preventing coupling noise between adjacent bit lines in different columns

Abstract

A semiconductor memory device capable of preventing coupling noise being generated between adjacent bit lines in different columns. The device comprises first and second columns, wherein each column comprises a pair of bit lines, and wherein the first and second columns are adjacent, first and second sense amplifiers, each being connected to the bit lines of the first or second column, for sensing and amplifying a voltage difference between the bit lines of the first or second column, and a control circuit for controlling the first and second sense amplifiers. When the voltages of adjacent bit lines of the first and second columns transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifiers to concurrently amplify the voltages of the adjacent bit lines.

Claims19

Dependent claims

A semiconductor memory device, comprising:

first and second columns, wherein each column comprises a pair of bit lines, and wherein the first and second columns are adjacent;
a first sense amplifier, connected to the bit lines of the first column, for sensing and amplifying a voltage difference between the bit lines of the first column;
a second sense amplifier, connected to the bit lines of the second column, for sensing and amplifying a voltage difference between the bit lines of the second column;
and
a control circuit for controlling the first and second sense amplifiers, wherein when voltage levels of adjacent bit lines of the first and second columns transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifiers to concurrently amplify the voltages of the adjacent bit lines.

2 more elements

A semiconductor memory device, comprising:

an array of memory blocks each comprising a plurality of columns, each column comprising a pair of bit lines;
a plurality of sense amplifier blocks, wherein first and second sense amplifier blocks are disposed on opposite sides of a corresponding memory block, wherein each sense amplifier block comprises a plurality of sense amplifiers connected to columns of the corresponding memory block, wherein adjacent columns are connected to sense amplifiers on opposite sides of the memory block;
and
a control circuit for controlling the first and second sense amplifier blocks, wherein when voltage levels of adjacent bit lines of adjacent columns of a memory block transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifier blocks to concurrently amplify the voltages of the adjacent bit lines.

1 more element

A method for preventing coupling noise from being generated in a semiconductor memory device, the device comprising first and second columns each comprising a pair of bit lines, comprising the steps of:

sensing voltage differences between the bit lines in the first and second columns, respectively;
and
concurrently amplifying voltage of adjacent bit lines of the first and second columns, when the voltage levels of the adjacent bit lines of the first and second columns transition in an opposite direction during a read operation.

Dependencies are inferred from the claim text.

Semiconductor memory device capable of preventing coupling noise between adjacent bit lines in different columns

Life of this patent

Semiconductor memory device capable of preventing coupling noise between adjacent bit lines in different columns

Life of this patent

Abstract

Claims19