Semiconductor memory and output signal control method and circuit in semiconductor memory
AssigneeFujitsu Limited
InventorKazuhide Kurosaki
Life of this patent
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Abstract
A signal delay circuit (100) is provided for inhibiting an output control signal (/OE), which is externally input, from transferring to an output buffer (6) for a predetermined period after an address change. While a sense amplifier (1) senses data in the predetermined period after the address changes, the logic level of a signal (OUT) output from the output buffer (6) is inhibited from being inverted. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier (1).
Claims4
A semiconductor memory wherein polling data and read data are selectively switched by a polling signal and output via an output buffer in an automatic algorithm operation of a write/erase, said memory comprising delay unit for delaying data-switching based on the polling signal by a predetermined period.
A semiconductor memory to operate by an automatic algorithm of a write/erase, said memory comprising delay unit for delaying switching from polling data to read data while a sense amplifier performs a data sense operation in switching data from polling data to read data to be transferred to an output buffer by changing an address from a given block to another block in a suspend read performed in operating by said automatic algorithm.
An output signal control method in a semiconductor memory wherein polling data and read data are selectively switched by a polling signal and output via an output buffer in operating by an automatic algorithm of a write/erase, said method comprising the step of delaying data-switching based on said polling signal by a predetermined period.
An output signal control circuit wherein polling data and read data are selectively switched by a polling signal and output via an output buffer in a semiconductor memory operating by an automatic algorithm of a write/erase, said circuit comprising delay unit for delaying data-switching based on said polling signal by a predetermined period.
Dependencies are inferred from the claim text.