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US 2003/0117861 A1Published application
NROM NOR array
AssigneeSaifun Semiconductors Ltd.
InventorsEduardo Maayan, Boaz Eitan
Life of this patent
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Abstract
A NOR array includes a first plurality of word lines, a second plurality of bit lines and a third plurality of common lines. Each word line connects to the gates of a row of nitride read only memory (NROM) cells. Each bit line connects to one diffusion area of each NROM cell in a column of the NROM cells and each common line connects to the other diffusion areas of each NROM cell in a row of the NROM cells.
Claims23
A NOR array comprising:
- a first plurality of word lines, each word line connecting to the gates of a row of nitride read only memory (NROM) cells;
- a second plurality of bit lines, each bit line connecting to one diffusion area of each NROM cell in a column of said NROM cells;
- and
- a third plurality of common lines, each common line connecting to the other diffusion areas of each NROM cell in a row of said NROM cells.
1 more element
A memory array comprising:
- a plurality of memory cells each capable of storing at least one EEPROM bit and at least one FLASH EEPROM bit.
A memory array comprising:
- a first plurality of memory cells each capable of storing at least one EEPROM bit;
- and
- a second plurality of select transistors each of which select a group of more than one of said memory cells.
A method comprising:
- having a plurality of memory cells in a NOR memory array, wherein each said cell has bit line and common line storage areas, wherein said bit line storage areas area connected to one of a second plurality of bit lines and wherein said common line storage areas are connected to one of a third plurality of common lines;
- reading said bit line storage areas with a close to ground sense amplifier;
- and
- reading said common line storage areas with a non-close to ground sense amplifier.
1 more element
A method comprising:
- having a plurality of memory cells in a NOR memory array, wherein each memory cell has one storage area connected to one of a second plurality of bit lines;
- and
- reading said bit line storage areas with a sense amplifier that has a close to ground input level.
Dependencies are inferred from the claim text.