Active leakage control in single-ended full-swing caches

A memory device, the memory device comprising:

• a bit line;
• a set of memory cells, each memory cell comprising:
• a read-pass transistor having a source and a drain;
• a read-select transistor having a drain connected to the bit line and a source connected to the drain of the read-pass transistor;
• and
• a foot transistor having a drain connected to the source of each read-pass transistor;
• wherein the foot transistor is ON during a read operation on one of the memory cells, and wherein the foot transistor is OFF when there is no read operation on any of the memory cells.

A memory device comprising:

• a plurality of memory cells, each memory cell comprising a read-pass transistor having a source and a drain, and comprising a read-access transistor having a drain and having a source connected to the drain of the read-pass transistor;
• where the plurality of memory cells are grouped into sets of memory cells, where each set of memory cells is grouped into subsets of memory cells;
• and
• a plurality of foot transistors in one-to-one correspondence with the subsets of memory cells, each foot transistor having a drain connected to the source of each read-pass transistor in the corresponding subset of memory cells;
• wherein during a read operation on a particular memory cell belonging to a particular subset of memory cells belonging to a particular set of memory cells, the foot transistor connected to the read-pass transistors in the particular subset of memory cells is ON, where a foot transistor is OFF if connected to a subset of memory cells in which no read operation is performed.

A memory device to read stored data addressable by an n-bit address, the memory device comprising:

• a plurality of 2n memory cells, each memory cell comprising a read-pass transistor having a source and a drain, and comprising a read-access transistor having a drain and having a source connected to the drain of the read-pass transistor;
• where the plurality of 2n memory cells are grouped into 2m sets of 2n−m memory cells, where 0≦m≦n, where each set of 2n−m memory cells is grouped into 2k subsets of memory cells so that there are 2m+k subsets of memory cells, where 0≦k≦n−m, each subset of memory cells having 2n−m−k memory cells;
• a plurality of 2m+k foot transistors in one-to-one correspondence with the 2m+k subsets of memory cells, each foot transistor having a drain connected to the source of each read-pass transistor in the corresponding subset of memory cells;
• and
• a decoder coupled to the pluralities of memory cells and foot transistors, such that during a read operation on a particular memory cell belonging to a particular subset of 2n−m−k memory cells belonging to a particular set of 2n−mmemory cells, the foot transistor connected to read-pass transistors in the particular subset of 2n−m−k memory cells is ON, where a foot transistor is OFF if connected to a subset of 2n−m−k memory cells in which no read operation is performed.