Method of erasing a flash memory cell
AssigneeHyundai Electronics Industries Co., Ltd.
InventorHee Youl Lee
Life of this patent
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Abstract
Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.
Claims15
A method of erasing a flash memory cell including:
- (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain and (e) a well, the gate including:
- (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate, the method comprising the steps of:
- floating the source and the drain;
- applying a negative bias voltage to the control gate;
- applying a positive bias voltage to the well to thereby create a positive bias voltage in the source and the drain;
- applying a ground voltage to the well at a first time while maintaining the negative bias voltage a the control gate;
- and
- subsequently applying a ground voltage to the control gate.
A method of erasing a flash memory cell including:
- (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain and (e) a well, the gate including:
- (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate, the method comprising the steps of:
- applying a negative bias voltage to the control gate;
- applying a positive bias voltage to the well;
- creating a positive bias voltage in the source and the drain;
- applying a ground voltage to the control gate;
- and
- simultaneously floating the well, the source and the drain at a time.
A method of erasing a flash memory cell including:
- (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a P-well formed in the semiconductor substrate and (f) a N-well formed in the semiconductor substrate, the gate including:
- (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate, the method comprising the steps of:
- floating the N-well, the source and the drain;
- applying a negative bias voltage to the control gate;
- applying a positive bias voltage to the P-well;
- applying a ground voltage to the P-well;
- applying a ground voltage to the control gate;
- creating a ground voltage at the source and the drain;
- and
- applying a ground voltage to the N-well.
A method of erasing a flash memory cell including:
- (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including:
- (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate, the method comprising the steps of:
- floating the source and the drain;
- applying a positive bias voltage to the control gate;
- applying a negative bias voltage to the well to thereby create a negative bias voltage in the source and the drain;
- applying a ground voltage to the well at a first time while maintaining the positive bias voltage at the control gate;
- and
- subsequently applying a ground voltage to the control gate.
Dependencies are inferred from the claim text.