Dual cell reading and writing technique
OwnerRaul-Adrian Cerneainventor
Life of this patent
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Abstract
The cells of a memory cell array are programmed in a pair wise manner. The pairs are separated by at least one memory cell, reducing the possibility of interference between the pairs during programming. The memory cells are programmed individually by applying a relatively high voltage to one of the bit lines of each cell regardless whether the cells are to be programmed or not, while applying a lower voltage to the second bit lines, depending on whether the cells are to be programmed or not. This programming voltage assignment enhances the speed of programming. Furthermore, the pair wise programming scheme applies the necessary high voltages only half as often as in previous schemes to program all the cells of the array, increasing the lifetime of the memory system.
Claims28
A method of programming one or more memory cells that individually comprise a first diffusion and a second diffusion, comprising
- applying a first voltage to the first diffusion, sufficient to enable programming the memory cell, independent of whether the memory cell is to be programmed or not;
- and
- simultaneously applying a second or a third voltage to the second diffusion according to whether the memory cell is to be programmed or not,
- wherein the second voltage is less than the first voltage.
In an array of memory cells arranged in rows and columns that comprises bit lines extending in a direction along the columns, a method of programming the memory cells, comprising:
- identifying, for simultaneous programming, a plurality of pairs of first and second adjacent memory cells along a row with at least one cell positioned between adjacent pairs, said pairs individually comprising a shared bit line between them, a first bit line coupled to the first cell and a second bit line coupled to the second cell;
- applying a first voltage to the shared bit lines of the individual pairs that is sufficient to enable the programming of the pairs' first and second cells;
- and
- applying either a second or a third voltage to each of the first and second bit lines of the individual pairs according to whether the respective first or second cells are to be programmed or not.
In an array of memory cells arranged in rows and columns that comprises steering lines extending in a direction along the columns, a method of programming the memory cells:
- identifying, for simultaneous programming, a plurality of pairs of first and second adjacent memory cells along a row with at least one cell positioned between adjacent pairs;
- and
- applying either a first or a second voltage to each of the steering lines of the individual pairs according to whether the respective first or second cells are to be programmed or not.
In an array of memory cells arranged in rows and columns that comprises steering lines extending in a direction along the columns, the memory cells being coupled individually to two steering lines, a method of programming the memory cells:
- identifying, for simultaneous programming, a plurality of pairs of first and second adjacent memory cells along a row with at least one cell positioned between adjacent pairs, said pairs individually comprising two adjacent steering lines and a first steering line coupled to the first cell and a second steering line coupled to the second cell;
- applying a first voltage to the adjacent steering lines of the individual pairs that is sufficient to enable the programming of the pairs' first and second cells;
- and
- applying either a second or a third voltage to each of the first and second steering lines of the individual pairs according to whether the respective first or second cells are to be programmed or not.
In an array of memory cells arranged in rows and columns that comprises bit lines extending in a direction along the columns, a method of reading the memory cells, comprising:
- identifying, for simultaneous reading, a plurality of pairs of first and second adjacent memory cells along a row with at least one cell positioned between adjacent pairs, said pairs individually including a shared bit line between them, a first bit line coupled to the first cell and a second bit line coupled to the second cell;
- applying a first voltage to the shared bit lines of the individual pairs that is sufficient to enable the reading of the pairs' first and second cells;
- applying a second voltage to the first and second bit lines of the individual pairs, sufficient to enable the reading of the pairs' first and second cells;
- and
- sensing the current, generated through the first and second bit lines of the individual pairs, to read the memory cells.
Dependencies are inferred from the claim text.