Operation verification system and adaptive control system

An operation verification system including:

• a normal operation circuit that is constituted by a clock generation unit for generating a clock for an internal operation, a first memory element as a target of operation verification, and an arithmetic circuit group which comprises arithmetic circuits other than the first memory element;
• and
• an operation verification circuit that is constituted by a delay circuit for delaying data outputted from the arithmetic circuit group, which is to be latched by the first memory element, a second memory element that stores data delayed by the delay circuit, in accordance with a clock having a same phase as that of the first memory element, and a judgement unit for judging whether the normal operation circuit is operating stably or not on the basis of results outputted from the first and second memory elements,
• said operation verification system monitoring an output from the judgement unit, to perform verification of a high-speed operation of the first memory element, at a low operation frequency.

An operation verification system including:

• a normal operation circuit that is constituted by a clock generation unit for generating a clock for an internal operation, a first memory element as a target of operation verification, and an arithmetic circuit group which comprises arithmetic circuits other than the first memory element;
• and
• an operation verification circuit that is constituted by a delay circuit for delaying data outputted from the arithmetic circuit group, which is to be latched by the first memory element, a second memory element that stores data delayed by the delay circuit, in accordance with a clock having a different phase from that of the first memory element, and a judgement unit for judging whether the normal operation circuit is operating stably or not on the basis of results outputted from the first and second memory elements,
• said operation verification system monitoring an output from the judgement unit, to perform verification of a high-speed operation of the first memory element, at a low operation frequency.