Flash memory device

Abstract

The present invention relates to a flash memory device for read-out. The flash memory device comprises a pumping circuit for generating a pumping voltage higher than the power supply voltage depending on an enable signal generated when a standby mode, a read-out mode and a power supply voltage are set up, a capacitor for charging the potential depending on the pumping voltage of the pumping circuit, a word line decoder and a bit line decoder for decoding an address signal to select a word line and a bit line of a given cell from the flash memory cell array, and a word line driver and a bit line driver for applying a given voltage depending on an electric charge stored at the capacitor to the word line and the bit line of the selected cell in the flash memory cell array so that a read-out operation is performed. At this time, a voltage depending on the charge stored at the capacitor is applied to the word line driver and the bit line driver in the read-out mode. Therefore, lowering in the read-out speed by loading of the word line can be significantly improved.

Dependencies are inferred from the claim text.