NAND-type flash memory device with multi-page program, multi-page read, multi-block erase operations

A NAND-type flash memory device comprising:

• a plurality of mats each including a plurality of memory blocks,
• wherein each of the memory blocks includes a plurality of memory cells arranged in a matrix of rows and columns;
• a plurality of row selectors each corresponding to the memory blocks of the respective mats and each selecting a corresponding memory block in response to block selection information;
• a plurality of page buffer circuits corresponding to the plurality of mats and each sensing data from a selected memory block of a corresponding mat through columns of a selected memory block and transferring data to be programmed to the columns of the selected memory block;
• a plurality of column selectors corresponding to the plurality of mats and each partially selecting the columns of the selected memory block;
• a plurality of pass/fail check circuits corresponding to the plurality of mats and each determining whether data transferred from a corresponding buffer circuit through a column selector is pass data;
• a plurality of reset signal generators corresponding to the plurality of mats and generating a first reset signal of a corresponding mat when the transferred data is the pass data;
• and
• a latch signal generator for selecting one of the mats in response to mat selection information,
• wherein each of the row selectors includes:
• a decoding circuit for generating a block selection signal in response to the block selection information;
• a register for storing an output of the decoding circuit when a latch signal of a corresponding mat is activated;
• a first switch for transferring a high voltage to a block wordline when a value latched by the register indicates that a corresponding memory block is selected, the first switch being coupled to the block wordline;
• a second switch for transferring wordline voltages to rows of a corresponding memory block in response to the high voltage on the block wordline;
• and
• a reset circuit for resetting the register when the first reset signal is activated.