Back to results
US 2003/0117842 A1Published application
Semiconductor device
AssigneeHitachi, Ltd.
InventorsSatoru Hanzawa, Takeshi Sakata
Life of this patent
Estimating the term…
Abstract
A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
Claims23
A semiconductor device comprising:
- a plurality of first memory cells for storing either one of first information and second information, arranged at points of intersection between a plurality of word lines and a plurality of first data lines;
- a plurality of first dummy cells for storing said first information, arranged at points of intersection between said plurality of word lines and first dummy data lines;
- and
- a plurality of second dummy cells for storing said second information, arranged at points of intersection between said plurality of word lines and second dummy data lines.
1 more element
A semiconductor device comprising:
- a plurality of first memory cells arranged at points of intersection between a plurality of word lines and a plurality of first data lines;
- a plurality of second memory cells arranged at points of intersection between said plurality of word lines and a plurality of second data lines;
- a plurality of first dummy cells arranged at points of intersection between said plurality of word lines and first dummy data lines;
- a plurality of second dummy cells arranged at points of intersection between said plurality of word lines and second dummy data lines;
- a plurality of third memory cells arranged at points of intersection between said plurality of word lines and a plurality of third data lines;
- a plurality of fourth memory cells arranged at points of intersection between said plurality of word lines and a plurality of fourth data lines;
- a plurality of third dummy cells arranged at points of intersection between said plurality of word lines and a plurality of third dummy data lines;
- a plurality of fourth dummy cells arranged at points of intersection between said plurality of word lines and a plurality of fourth dummy data lines;
- a first multiplexer connected to said plurality of first and second data lines;
- a second multiplexer connected to said first and second dummy data lines;
- a third multiplexer connected to said plurality of third and fourth data lines;
- a first common data line to which said plurality of first data lines are connected through said first multiplexer;
- a second common data line to which said plurality of second data lines are connected through said first multiplexer;
- a third common data line to which said plurality of third data lines are connected through said third multiplexer;
- a fourth common data line to which said plurality of fourth data lines are connected through said fourth multiplexer;
- a first switch connected between said first and third common data lines;
- a second switch connected between said second and fourth common data lines;
- a first read circuit connected between said first and second common data lines;
- and
- a second read circuit connected between said third and fourth common data lines;
- wherein:
- memory information mutually complementary are written to said plurality of first dummy cells and said plurality of second dummy cells;
- memory information mutually complementary are written to said plurality of third dummy cells and said plurality of fourth dummy cells;
- said first dummy data line is connected to said first common data line through said second multiplexer;
- said second dummy data line is connected to said third common data line through said second multiplexer;
- said third dummy data line is connected to said second common data line through said fourth multiplexer;
- and
- said fourth dummy data line is connected to said fourth common data line through said fourth multiplexer.
25 more elements
Dependencies are inferred from the claim text.