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US 2003/0117833 A1Published application
Sram power-up system and method
AssigneeMicron Technology, Inc.
InventorKen W. Marr
Life of this patent
Estimating the term…
Abstract
A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.
Claims53
An SRAM cell array, comprising:
- an array of SRAM cells arranged in rows and columns, the array including a wordline for each row of the array and a pair of complementary digit lines for each column of the array, each of the SRAM cells having an a pair of access transistors coupled to respective complementary digit lines for a respective column and a gate coupled to a wordline for a respective row;
- and
- a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access transistors non-conductive in a power-up mode.
An SRAM cell array, comprising:
- an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;
- a wordline coupled to the control terminal of each of the access switches in a respective row;
- a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;
- a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- and
- a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode.
5 more elements
A static random access memory (“SRAM”) comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- the memory-cell array comprising:
- an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;
- a wordline coupled to the control terminal of each of the access switches in a respective row;
- a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;
- a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- and
- a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode;
- and
- a control circuit operable to control the operation of the SRAM.
14 more elements
A computer system, comprising:
- a processor having a processor bus;
- at least one input device coupled to the processor through the processor bus;
- at least one output device coupled to the processor through the processor bus;
- at least one data storage devices coupled to the processor through the processor bus
- a system memory coupled to the processor through the processor bus;
- and
- an static random access cache memory coupled to the processor through the processor bus, the static random access cache memory comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- the memory-cell array comprising:
- an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;
- a wordline coupled to the control terminal of each of the access switches in a respective row;
- a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;
- a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- and
- a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines;
- a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode;
- and
- a control circuit operable to control the operation of the SRAM.
21 more elements
In an array of SRAM cells arranged in rows and columns and having a pair of complementary digit lines for each column of the array coupled to respective access transistors for each SRAM cell, a method of controlling the power-up current drawn by the array, comprising:
- applying a predetermined bias current to the digit lines in a normal mode;
- and
- coupling the digit lines to a voltage that maintains the access transistors nonconductive in a power-up mode.
Dependencies are inferred from the claim text.