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US 2003/0117832 A1Published application
Semiconductor memory device having two-transistor, one-capacitor type memory cells of high data holding characteristic
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorShigeki Tomishima
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Abstract
An active region which forms two transistors included in a memory cell is arranged to have a strip shape along a predetermined axis crossing first and second bit lines at less than 90 degrees, whereby it is possible to reduce a junction area corresponding to a connection node of connecting the two transistors between the active region and a substrate and to reduce a leak current.
Claims10
A semiconductor memory device comprising:
- a memory array in which a plurality of memory cells are arranged in a matrix, wherein
- said memory array includes
- a plurality of first and second bit lines provided to correspond to memory cell columns, respectively, and
- a plurality of first and second word lines provided to correspond to memory cell rows, respectively;
- said semiconductor memory device further comprising:
- a plurality of first sense amplifiers connected to at least one of said plurality of first bit lines in a region adjacent to said memory array in a row direction, respectively;
- and
- a plurality of second sense amplifiers connected to at least one of said plurality of second bit lines in a region opposite to said plurality of first sense amplifiers across said memory array, respectively;
- and wherein
- each of said plurality of memory cells has
- a first transistor connected between corresponding one of said plurality of first bit lines and a storage node,
- a second transistor connected between corresponding one of said plurality of second bit lines and said storage node, and
- a capacitor connected to said storage node to hold charges as data.
10 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of memory cells arranged in a matrix, wherein
- each of said plurality of memory cells includes:
- a capacitor storing data by accumulating charges;
- and
- first and second transistors provided on a shared active region, respectively, and electrically connected between a storage node connected to said capacitor, and a first bit line and between the storage node and a second bit line said first and second lines being arranged to correspond to memory cell columns in parallel to each other, respectively, and wherein
- gates of said first and second transistors are connected to first and second word lines provided to correspond to memory cell rows along a direction crossing with said first and second bit lines, respectively, and
- said shared active region is arranged to have an elongate shape along a predetermined axis crossing with said first and second bit lines so as to form a predetermined angle of less than 90 degrees with respect to said first and second bit lines.
4 more elements
Dependencies are inferred from the claim text.