Programmable conductor random access memory and a method for writing thereto

A method for writing a semiconductor memory cell, the method comprising:

• applying a first predetermined voltage to a first terminal of a programmable conductor memory element;
• charging a bit line of a memory array to which said memory cell belongs to a second predetermined voltage, said bit line having a parasitic capacitance which stores said second predetermined voltage;
• applying a third predetermined voltage to a gate of a transistor to enable said transistor and couple said bit line to a second terminal of said programmable conductor memory element;
• and
• using a voltage across said memory element when said transistor is enabled to establish a resistance state of said memory element.

A method of operating a memory cell, said method comprising:

• precharging a bit line to a first voltage;
• applying a second voltage to a first terminal of a chalcogenide memory element;
• and
• connecting a second terminal of said chalcogenide memory element to said bit line to produce a voltage across said memory element sufficient to write a predetermined resistance state into said memory element.

A memory structure comprising:

• a conductor having an associated capacitance;
• a precharge circuit for precharging said conductor to a first voltage, said first voltage being held on said conductor by said associated capacitance;
• a programmable conductor memory element having one terminal connected to a second voltage;
• and
• an access device for selectively coupling a second terminal of said memory element to said conductor, said access device enabling said first and second voltages to establish a voltage across said programmable element sufficient to program said memory element to one of a higher and lower resistance state.

A semiconductor memory comprising:

• a bit line having an associated capacitance;
• a programmable conductor memory element having first and second terminals;
• a precharge circuit for precharging said bit line to one of two possible voltage values depending on a desired state of resistance programming of said memory element, said associated capacitance holding a precharge voltage value on said bit line;
• a cell plate coupled to a first terminal of said memory element for supplying a third voltage value to said first terminal;
• and
• an access transistor responsive to a voltage on a word line for selectively coupling said bit line to said second terminal of said memory element to program said memory element to a resistance state based on the voltage values on said cell plate and bit line.

A memory cell comprising:

• a chalcogenide memory element having first and second terminals;
• a first memory line;
• a circuit for selectively precharging said first memory line to either a first or second voltage;
• a circuit for supplying a third voltage to the first terminal of said chalcogenide element;
• and
• a device for switchably coupling the second terminal of said chalcogenide memory element to said first memory line after said first memory line has been precharged, said device causing a voltage to be applied across said chalcogenide memory element sufficient o write one of two predetermined resistance states in said chalcogenide element depending on which of said first or second voltage is precharged on said memory line.

A processor system comprising:

• a processor;
• and
• a semiconductor memory coupled to said processor, said semiconductor memory comprising:
• a conductor having an associated capacitance;
• a precharge circuit for precharging said conductor to a first voltage, said first voltage being held on said conductor by said associated capacitance;
• a programmable conductor memory element having one terminal connected to a second voltage;
• and
• an access device for selectively coupling a second terminal of said memory element to said conductor, said access device enabling said first and second voltages to establish a voltage across said programmable element sufficient to program said memory element to one of a higher and lower resistance state.