Semiconductor memory device and write/readout controlling method error correction code decoding device

A semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in an array:

• and
• a plurality of selection transistors arranged respectively on one side and on another side opposing to said one side of sad memory cell array;
• wherein
• two electrically conductive regions formed in separation from each other on the substrate surface are interconnected to form a set of sub bit lines, the set of the sub bit lines being connected to one main bit line via an associated one of the selection transistors;
• and wherein
• there are arranged, in a region in the memory cell array area defined between a pair of electrically conductive regions composing one set of said sub bit lines, each one of paired electrically conductive regions forming two sets of sub bit lines respectively connected via selection transistors to two main bit lines on both sides adjacent to a main bit line associated with the set of the sub bit lines, and each one of paired electrically conductive regions forming two sets of sub bit lines respectively connected to the two neighboring main bit lines via selection transistors on the opposite side of the memory cell array, totaling at four sub bit lines.

A semiconductor memory device comprising:

• a first group of electrically conductive regions composed of a plural number of electrically conductive regions extending parallel to one another on a memory cell array region on a substrate surface, from one side of the memory cell array to the opposite side thereof, and a second group of electrically conductive regions composed of a plural number of electrically conductive regions extending parallel to one another from the other end to the one end of the memory cell array;
• each of a plurality of gate electrodes extending parallel to one another via an insulating film on the substrate surface in a direction perpendicular to a direction along which the electrically conductive regions are extended, each gate electrode composing a word line;
• two of the electrically conductive regions of the plural electrically conductive regions belonging to the same set being paired to form a set of sub bit lines;
• one of the paired electrically conductive regions forming one set of the sub bit lines being connected to one of the paired diffusion layers of the selection transistor, the gate of which is connected to a selection control line, the other diffusion layer of the selection transistor being connected to a main bit line formed on an upper layer on the substrate;
• the paired electrically conductive regions forming the set of the sub bit lines having respective ends on the side connected to the selection transistor (termed one side ends) via a contact to one wiring on an upper layer on the substrate;
• and wherein
• between the paired electrically conductive regions forming the set of the sub bit lines, there are arranged each one of paired electrically conductive regions forming two sets of the sub bit lines, connected via selection transistors to two main bit lines lying on both sides of the main bit line to which the set of the sub bit lines are connected via selection transistor and each one of paired electrically conductive regions forming two sets of the sub bit lines, respectively connected to two main bit lines neighboring to each other via a selection transistor lying opposite to the selection transistor connected to the set of the sub bit lines, totaling at four electrically conductive regions.

A semiconductor memory device comprising a first group of electrically conductive regions composed of a plural number of electrically conductive regions extending parallel to one another on a memory cell array region on a substrate surface from one side of the memory cell array to the opposite side thereof, and a second group of electrically conductive regions composed of a plural number of electrically conductive regions extending parallel to one another from the other end to the one end of the memory cell array;

• each of group of gate electrodes, each gate electrode extending parallel to one another via an insulating film on the substrate surface in a direction perpendicular to the extending direction of the electrically conductive regions, to form a word line;
• two of the electrically conductive regions of the plural electrically conductive regions belonging to the same group being paired to form a set of sub bit lines;
• one of the paired electrically conductive regions forming one set of the sub bit lines being connected to one of the paired diffusion layers of the selection transistor to the gate of which is connected a selection control line, the other diffusion layer of the selection transistor being connected to a main bit line on an upper layer on the substrate;
• the end of the paired electrically conductive regions forming the set of the sub bit lines, lying on the side of one electrically conductive region connected to the selection transistor (termed one side end) is connected via a contact to one wiring of the wiring layer on a upper substrate layer to the longitudinally opposite end of the other electrically conductive region;
• and wherein
• there are arranged, between the paired electrically conductive regions forming the set of the sub bit lines, each one of paired electrically conductive regions forming two sets of the sub bit lines, connected via selection transistors to two main bit lines lying on both sides of the main bit line to which the set of the sub bit lines are connected via selection transistor and each one of paired electrically conductive regions forming two sets of the sub bit lines, respectively connected to two main neighboring bit lines via a selection transistor connected to the set of the sub bit lines, totaling at four electrically conductive regions.

A method of controlling write operation in a semiconductor storage device in which a set of sub bit lines are formed by interconnecting a pair of electrically conductive regions extending parallel to each other on a substrate surface,

• a plurality of selection transistors for connecting a set of sub bit lines to an associated main bit line are arranged on both longitudinal end sides of a memory cell array;
• and in which
• a plurality of sets of sub bit lines respectively connected to the selection transistors arranged on one and on the other longitudinal end sides of the memory cell array are arranged alternately;
• said method comprising the steps of:
• applying a ground potential and a preset positive voltage to first and second ones of two neighboring electrically conductive regions associated with a selected memory cell, and a preset positive voltage to a gate electrode associated with the selected memory cell;
• and
• applying, when writing in the memory cell, a voltage between the positive voltage applied to the second electrically conductive region and the ground potential to a third electrically conductive region neighboring to the second electrically conductive region to which the positive voltage is applied, the third electrically conductive region lying on the opposite side to the first electrically conductive region.

A method of controlling write operation in a semiconductor storage device in which a set of sub bit lines are formed by interconnecting a pair of electrically conductive regions extending parallel to each other on a substrate surface,

• a plurality of selection transistors for connecting a set of sub bit lines to an associated main bit line are arranged on both longitudinal end sides of a memory cell array;
• and in which
• a plurality of sets of sub bit lines respectively connected to the selection transistors arranged on one and on the other longitudinal end sides of the memory cell array are arranged alternately;
• said method comprising the step of:
• applying a ground potential and a preset positive voltage to first and second ones of two electrically conductive regions associated with a selected memory cell, and a preset positive voltage to a gate electrode associated with the selected memory cell;
• and
• applying, when writing in the memory cell, a positive voltage of the same level as that of the second electrically conductive region, to an electrically conductive region neighboring to the second electrically conductive region supplied with the positive voltage, and to an electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region among the electrically conductive regions neighboring to a third by being electrically conductive region forming a set of the sub bit lines by paired to the second electrically conductive region;
• and
• applying a voltage between the positive voltage supplied with the positive voltage and the ground voltage to at least one of the first electrically conductive region and an electrically conductive region arranged between a fourth electrically conductive region forming a set of sub bit lines by being paired with the first electrically conductive region and the electrically conductive region to which is applied the positive voltage.

A method of controlling read operation in a semiconductor storage device in which a set of sub bit lines are formed by interconnecting a pair of electrically conductive regions extending parallel to each other on a substrate surface,

• a plurality of selection transistors for connecting a set of sub bit lines to an associated main bit line are arranged on both longitudinal end sides of a memory cell array;
• and in which
• a plurality of sets of sub bit lines respectively connected to the selection transistors arranged on one and on the other longitudinal end sides of the memory cell array are arranged in an interchanged fashion;
• the method comprising the steps of:
• applying a ground potential and a preset positive voltage respectively to first and second ones of two neighboring electrically conductive regions associated with a selected memory cell, and a preset positive voltage to a gate electrode associated with the selected memory cell;
• and
• applying, when reading out from the memory cell, a positive voltage of the same level applied to the second electrically conductive region to a third electrically conductive region neighboring to the second electrically conductive region to which the positive voltage is applied, the third electrically conductive region lying on the opposite side to the first electrically conductive region.

A method of controlling read operation in a semiconductor storage device in which a set of sub bit lines are formed by interconnecting two paired electrically conductive regions extending parallel to each other on a substrate surface,

• a plurality of selection transistors for connecting a set of sub bit lines to an associated main bit line are arranged on both longitudinal end sides of a memory cell array;
• and in which
• a plurality of sets of sub bit lines respectively connected to the selection transistors arranged on one and on the other longitudinal end sides of the memory cell array are arranged in an interchanged fashion;
• the method comprising the steps of:
• applying a ground potential and a preset positive voltage respectively to first and second ones of two neighboring electrically conductive regions associated with a selected memory cell, a preset positive voltage to the second electrically conductive region and a preset positive voltage to a gate electrode associated with the selected memory cell, and for applying, when reading out from the memory cell, a positive voltage of the same level as that of the second electrically conductive region, to an electrically conductive region neighboring to the second electrically conductive region supplied with the positive voltage, and to an electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region, the electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region being from the electrically conductive regions neighboring to a third by being electrically conductive region forming a set of the sub bit lines by paired to the second electrically conductive region;
• and
• applying a ground potential to at least one of the first electrically conductive region and an electrically conductive region arranged between a fourth electrically conductive region forming a set of sub bit lines by being paired with the first electrically conductive region and the electrically conductive region to which is applied the positive voltage.

A semiconductor memory device comprising:

• a plurality of electrically conductive regions extending parallel to one another on a substrate surface forming a memory cell region;
• wherein
• two of the electrically conductive regions are connected as a pair to form a set of sub bit lines;
• the one set of the sub bit lines being connected to a main bit line via a selection transistor;
• a plurality of the selection transistors are arranged opposing to one another on both sides of the memory cell array;
• the memory cell array is formed by a plurality of (M) sets, each set being composed of a plurality of (N) word lines as a unit;
• M sets of paired electrically conductive regions, forming said one set of sub bit lines, are arranged along two lines, corresponding to the M sets forming the memory cell array;
• for each of the M sets of paired electrically conductive regions, one end of one of the paired electrically conductive regions and another end of the other of the paired electrically conductive regions are interconnected via a wiring on an upper layer on the substrate, the another end being longitudinally opposite to the one end;
• and wherein
• the paired electrically conductive regions of each of the M sets are connected common to one of the selection transistors via the wiring on an upper layer on the substrate.

A semiconductor device comprising:

• a memory cell array region including a plurality of memory cells arranged in an array format on a substrate;
• a plurality of main bit lines;
• a plurality of selection transistors, each arranged between the main bit line and an associated set of sub bit lines, controlled on and off by a selection control signal;
• a plural number of electrically conductive regions extending parallel to one another on the memory cell array region on the substrate surface,
• said electrically conductive regions paired two by two to form a plural sets of sub bit lines, each set of sub bit lines connected via an associated one of the selection transistors to the main bit line,
• one end of one of paired electrically conductive regions forming one set of sub bit lines, diagonally interconnected to another end of the other of the paired electrically conductive regions via a wiring provided on an upper layer on the substrate, said another end being longitudinally opposite to said one end;
• and
• a plurality of gate electrodes extending parallel to one another via an insulating film on the substrate surface in the memory cell array region in a direction perpendicular to a direction along which the electrically conductive regions are extended, each gate electrode composing a word line, the memory cell being formed at an intersection area of the gate electrode and neighboring two electrically conductive regions.