US 2003/0117404 A1 · Image processing apparatus

Abstract

An image processing apparatus capable of achieving an increase of capacity and consequently capable of achieving an improvement of processing capability without causing a drop in performance and an increase of the cost. A built-in memory for storing image data and a logic circuit are accommodated on the same semiconductor chip, an external memory is additionally provided, the memory area of the external memory is divided into a plurality of blocks, predetermined data is stored in each of the blocks, the memory area of the built-in memory is divided into blocks each having the same capacity as that of a divided block of the external memory, and a memory I/F circuit displaces data which becomes unnecessary among the data stored in the built-in memory with the data needed next stored in the predetermined block of the external memory and accesses the data which becomes necessary newly stored in the built-in memory when certain data stored in the built-in memory becomes unnecessary and a displacement command is issued.

Claims6

Dependent claims

An image processing apparatus, comprising:

at least a built-in memory for storing image data,
an external memory for storing data regarding the image,
a logic circuit provided on the same semiconductor chip as the built-in memory and performing predetermined processing on the image data based on the stored data of the built-in memory and/or external memory, and
a memory interface circuit for controlling access of data between the built-in memory and external memory and the logic circuit.

1 more element

An image processing apparatus for performing rendering by receiving polygon rendering data including three-dimensional coordinates (x, y, z), R (Red), G (Green), and B (Blue) data, homogeneous coordinates (s, t) of texture, and a homogeneous term q for vertexes of a unit graphic, comprising:

a built-in memory for storing display data and texture data required by at least one graphic element;
a logic circuit provided with at least an interpolated data generation circuit for interpolating the polygon rendering data of the vertexes of the unit graphic to generate interpolated data of pixels positioned inside the unit graphic and a texture processing circuit for dividing the homogeneous coordinates (s, t) of texture included in the interpolated data by the homogeneous term q to generate “s/q” and “t/q”, reading texture data by using a texture address corresponding to the “s/q” and “t/q”, and performing processing to apply the texture data to a surface of graphic elements of the display data and accommodated with the built-in memory on a single semiconductor chip;
an external memory for storing at least the data regarding the texture processing;
and
a memory interface circuit for controlling the access of the data between the built-in memory and external memory and the logic circuit.

2 more elements

Dependencies are inferred from the claim text.

Image processing apparatus

Life of this patent

Image processing apparatus

Life of this patent

Abstract

Claims6