Active matrix display device and scanning circuit
AssigneeSemiconductor Energy Laboratory Co., Ltd., a Japanese corporation
InventorsKenichi Katoh, Yasushi Kubota, Hidehiko Chimura, Jun Koyama
Life of this patent
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Abstract
An active matrix display device has a number of pixels arranged in matrix form, signal lines for supplying display signals to the pixels, and a driver circuit for driving the signal lines. The driver circuit includes a frequency divider circuit for frequency-dividing input multi-phase clock signals, a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals, and a decoder circuit for selecting a desired one of the signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.
Claims8
An active matrix display device comprising:
- a number of pixels arranged in matrix form;
- signal lines for supplying display signals to the pixels;
- and
- a driver circuit for driving the signal lines, the driver circuit comprising:
- a frequency divider circuit for frequency-dividing input multi-phase clock signals;
- a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals;
- and
- a decoder circuit for selecting a desired one of the signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.
An active matrix display device comprising:
- a number of pixels arranged in matrix form;
- signal lines for supplying display signals to the pixels;
- and
- a driver circuit for driving the signal lines, the driver circuit comprising:
- a frequency divider circuit for frequency-dividing input multi-phase clock signals;
- a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals;
- a decoder circuit divided into a plurality of decoder circuit sections;
- and
- a gate circuit for selectively supplying the respective decoder circuit sections with outputs of the frequency divider circuit and the synchronous counter circuit,
- wherein each of the decoder circuit sections selects a desired one of the signal lines based on the selectively supplied outputs of the frequency divider circuit and the synchronous counter circuit.
Dependencies are inferred from the claim text.