Clock generating circuit

A clock generating circuit generating a clock signal comprising:

• an oscillator generating a reference clock signal;
• a first latch circuit, provided between first and second nodes, transmitting a level on said first node to said second node when said reference clock signal is at a first logic level and holding a level on said second node in response to transition of said reference clock signal from said first logic level to a second logic level;
• a second latch circuit, provided between said second node and an output node for outputting said clock signal, transmitting a level on said second node to said output node when said reference clock signal is at said second logic level and holding a level on said output node in response to transition of said reference clock signal from said second logic level to said first logic level;
• and
• a logic circuit, provided between said output node and said first node, and providing a complementary level of a level on said output node to said first node to generate said clock signal when an activating signal is at a first level, while transmitting a level on said output node to said first node to cease generation of said clock signal when the activating signal is at a second level.