Delay circuit with current steering output symmetry and supply voltage insensitivity

An apparatus for providing a differential output signal responsive to a differential input signal, comprising:

• first and second inputs respectively adapted to receive first and second waveform portions of said differential input signal;
• first and second outputs respectively adapted to output first and second waveform portions of said differential output signal;
• a first delay circuit coupled between said first input and said first output;
• a second delay circuit coupled between said second input and said second output;
• a first symmetry circuit coupled to said first delay circuit and cooperable therewith to produce a gain characteristic between said first input and said first output that provides said differential output signal first waveform portion with approximately symmetrical rising and falling edges;
• and
• a second symmetry circuit coupled to said second delay circuit and cooperable therewith to produce a gain characteristic between said second input and said second output that provides said differential output signal second waveform portion with approximately symmetrical rising and falling edges.

An apparatus for providing a differential output signal responsive to a differential input signal, comprising:

• first and second inputs respectively adapted to receive first and second waveform portions of said differential input signal;
• first and second outputs respectively adapted to output first and second waveform portions of said differential output signal;
• a first delay half circuit coupled between said first input and said first output and adapted to produces a first gain characteristic between said first input and said first output;
• a second delay half circuit coupled between said second input and said second output and adapted to produces a second gain characteristic between said second input and said second output, and wherein said delay half circuits are coupled at a common node;
• first and second current steering circuits coupled to said common node and cooperable to steer current from said common node to said delay half circuits.